init
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ef1ee1e003
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22
.gitattributes
vendored
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22
.gitattributes
vendored
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@ -0,0 +1,22 @@
|
|||
# Auto detect text files and perform LF normalization
|
||||
* text=auto
|
||||
|
||||
# Custom for Visual Studio
|
||||
*.cs diff=csharp
|
||||
*.sln merge=union
|
||||
*.csproj merge=union
|
||||
*.vbproj merge=union
|
||||
*.fsproj merge=union
|
||||
*.dbproj merge=union
|
||||
|
||||
# Standard to msysgit
|
||||
*.doc diff=astextplain
|
||||
*.DOC diff=astextplain
|
||||
*.docx diff=astextplain
|
||||
*.DOCX diff=astextplain
|
||||
*.dot diff=astextplain
|
||||
*.DOT diff=astextplain
|
||||
*.pdf diff=astextplain
|
||||
*.PDF diff=astextplain
|
||||
*.rtf diff=astextplain
|
||||
*.RTF diff=astextplain
|
||||
215
.gitignore
vendored
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215
.gitignore
vendored
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|
|
@ -0,0 +1,215 @@
|
|||
#################
|
||||
## Eclipse
|
||||
#################
|
||||
|
||||
*.pydevproject
|
||||
.project
|
||||
.metadata
|
||||
bin/
|
||||
tmp/
|
||||
*.tmp
|
||||
*.bak
|
||||
*.swp
|
||||
*~.nib
|
||||
local.properties
|
||||
.classpath
|
||||
.settings/
|
||||
.loadpath
|
||||
|
||||
# External tool builders
|
||||
.externalToolBuilders/
|
||||
|
||||
# Locally stored "Eclipse launch configurations"
|
||||
*.launch
|
||||
|
||||
# CDT-specific
|
||||
.cproject
|
||||
|
||||
# PDT-specific
|
||||
.buildpath
|
||||
|
||||
|
||||
#################
|
||||
## Visual Studio
|
||||
#################
|
||||
|
||||
## Ignore Visual Studio temporary files, build results, and
|
||||
## files generated by popular Visual Studio add-ons.
|
||||
|
||||
# User-specific files
|
||||
*.suo
|
||||
*.user
|
||||
*.sln.docstates
|
||||
|
||||
# Build results
|
||||
|
||||
[Dd]ebug/
|
||||
[Rr]elease/
|
||||
x64/
|
||||
build/
|
||||
[Bb]in/
|
||||
[Oo]bj/
|
||||
|
||||
# MSTest test Results
|
||||
[Tt]est[Rr]esult*/
|
||||
[Bb]uild[Ll]og.*
|
||||
|
||||
*_i.c
|
||||
*_p.c
|
||||
*.ilk
|
||||
*.meta
|
||||
*.obj
|
||||
*.pch
|
||||
*.pdb
|
||||
*.pgc
|
||||
*.pgd
|
||||
*.rsp
|
||||
*.sbr
|
||||
*.tlb
|
||||
*.tli
|
||||
*.tlh
|
||||
*.tmp
|
||||
*.tmp_proj
|
||||
*.log
|
||||
*.vspscc
|
||||
*.vssscc
|
||||
.builds
|
||||
*.pidb
|
||||
*.log
|
||||
*.scc
|
||||
|
||||
# Visual C++ cache files
|
||||
ipch/
|
||||
*.aps
|
||||
*.ncb
|
||||
*.opensdf
|
||||
*.sdf
|
||||
*.cachefile
|
||||
|
||||
# Visual Studio profiler
|
||||
*.psess
|
||||
*.vsp
|
||||
*.vspx
|
||||
|
||||
# Guidance Automation Toolkit
|
||||
*.gpState
|
||||
|
||||
# ReSharper is a .NET coding add-in
|
||||
_ReSharper*/
|
||||
*.[Rr]e[Ss]harper
|
||||
|
||||
# TeamCity is a build add-in
|
||||
_TeamCity*
|
||||
|
||||
# DotCover is a Code Coverage Tool
|
||||
*.dotCover
|
||||
|
||||
# NCrunch
|
||||
*.ncrunch*
|
||||
.*crunch*.local.xml
|
||||
|
||||
# Installshield output folder
|
||||
[Ee]xpress/
|
||||
|
||||
# DocProject is a documentation generator add-in
|
||||
DocProject/buildhelp/
|
||||
DocProject/Help/*.HxT
|
||||
DocProject/Help/*.HxC
|
||||
DocProject/Help/*.hhc
|
||||
DocProject/Help/*.hhk
|
||||
DocProject/Help/*.hhp
|
||||
DocProject/Help/Html2
|
||||
DocProject/Help/html
|
||||
|
||||
# Click-Once directory
|
||||
publish/
|
||||
|
||||
# Publish Web Output
|
||||
*.Publish.xml
|
||||
*.pubxml
|
||||
|
||||
# NuGet Packages Directory
|
||||
## TODO: If you have NuGet Package Restore enabled, uncomment the next line
|
||||
#packages/
|
||||
|
||||
# Windows Azure Build Output
|
||||
csx
|
||||
*.build.csdef
|
||||
|
||||
# Windows Store app package directory
|
||||
AppPackages/
|
||||
|
||||
# Others
|
||||
sql/
|
||||
*.Cache
|
||||
ClientBin/
|
||||
[Ss]tyle[Cc]op.*
|
||||
~$*
|
||||
*~
|
||||
*.dbmdl
|
||||
*.[Pp]ublish.xml
|
||||
*.pfx
|
||||
*.publishsettings
|
||||
|
||||
# RIA/Silverlight projects
|
||||
Generated_Code/
|
||||
|
||||
# Backup & report files from converting an old project file to a newer
|
||||
# Visual Studio version. Backup files are not needed, because we have git ;-)
|
||||
_UpgradeReport_Files/
|
||||
Backup*/
|
||||
UpgradeLog*.XML
|
||||
UpgradeLog*.htm
|
||||
|
||||
# SQL Server files
|
||||
App_Data/*.mdf
|
||||
App_Data/*.ldf
|
||||
|
||||
#############
|
||||
## Windows detritus
|
||||
#############
|
||||
|
||||
# Windows image file caches
|
||||
Thumbs.db
|
||||
ehthumbs.db
|
||||
|
||||
# Folder config file
|
||||
Desktop.ini
|
||||
|
||||
# Recycle Bin used on file shares
|
||||
$RECYCLE.BIN/
|
||||
|
||||
# Mac crap
|
||||
.DS_Store
|
||||
|
||||
|
||||
#############
|
||||
## Python
|
||||
#############
|
||||
|
||||
*.py[co]
|
||||
|
||||
# Packages
|
||||
*.egg
|
||||
*.egg-info
|
||||
dist/
|
||||
build/
|
||||
eggs/
|
||||
parts/
|
||||
var/
|
||||
sdist/
|
||||
develop-eggs/
|
||||
.installed.cfg
|
||||
|
||||
# Installer logs
|
||||
pip-log.txt
|
||||
|
||||
# Unit test / coverage reports
|
||||
.coverage
|
||||
.tox
|
||||
|
||||
#Translations
|
||||
*.mo
|
||||
|
||||
#Mr Developer
|
||||
.mr.developer.cfg
|
||||
2
_ngo/netlist.lst
Normal file
2
_ngo/netlist.lst
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
C:\fpga\pong\main.ngc 1361499661
|
||||
OK
|
||||
9
_xmsgs/bitgen.xmsgs
Normal file
9
_xmsgs/bitgen.xmsgs
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
12
_xmsgs/map.xmsgs
Normal file
12
_xmsgs/map.xmsgs
Normal file
|
|
@ -0,0 +1,12 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
9
_xmsgs/ngdbuild.xmsgs
Normal file
9
_xmsgs/ngdbuild.xmsgs
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
</messages>
|
||||
|
||||
18
_xmsgs/par.xmsgs
Normal file
18
_xmsgs/par.xmsgs
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">VGADriver/W</arg> may have excessive skew because
|
||||
<arg fmt="%d" index="2">2</arg> CLK pins and <arg fmt="%d" index="3">0</arg> NON_CLK pins failed to route using a CLK template.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
15
_xmsgs/pn_parser.xmsgs
Normal file
15
_xmsgs/pn_parser.xmsgs
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated -->
|
||||
<!-- by the Xilinx ISE software. Any direct editing or -->
|
||||
<!-- changes made to this file may result in unpredictable -->
|
||||
<!-- behavior or data corruption. It is strongly advised that -->
|
||||
<!-- users do not edit the contents of this file. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<messages>
|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "C:/fpga/pong/vga.vhd" into library work</arg>
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
21
_xmsgs/trce.xmsgs
Normal file
21
_xmsgs/trce.xmsgs
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
|
||||
|
||||
<msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
34
_xmsgs/xst.xmsgs
Normal file
34
_xmsgs/xst.xmsgs
Normal file
|
|
@ -0,0 +1,34 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Xst" num="819" delta="old" >"<arg fmt="%s" index="1">C:/fpga/pong/main.vhd</arg>" line <arg fmt="%d" index="2">57</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
||||
<arg fmt="%s" index="3"><w>, <x>, <y></arg>
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="1305" delta="old" >Output <<arg fmt="%s" index="1">LED</arg>> is never assigned. Tied to value <arg fmt="%s" index="2">00000000</arg>.
|
||||
</msg>
|
||||
|
||||
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal <<arg fmt="%s" index="2">inrgb</arg>>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">7</arg>> in Unit <<arg fmt="%s" index="2">LPM_LATCH_1</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><6> <5> <1> <0> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">4</arg>> in Unit <<arg fmt="%s" index="2">LPM_LATCH_1</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><3> <2> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">VGADriver/RGB_4</arg>> in Unit <<arg fmt="%s" index="2">main</arg>> is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><VGADriver/RGB_3> <VGADriver/RGB_2> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch <<arg fmt="%s" index="1">VGADriver/RGB_7</arg>> in Unit <<arg fmt="%s" index="2">main</arg>> is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4"><VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_1> <VGADriver/RGB_0> </arg>
|
||||
</msg>
|
||||
|
||||
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
14
clockadjust.vhd
Normal file
14
clockadjust.vhd
Normal file
|
|
@ -0,0 +1,14 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity clockadjust is
|
||||
end clockadjust;
|
||||
|
||||
architecture Behavioral of clockadjust is
|
||||
|
||||
begin
|
||||
|
||||
|
||||
end Behavioral;
|
||||
|
||||
0
ggg.ucf
Normal file
0
ggg.ucf
Normal file
215
iseconfig/main.xreport
Normal file
215
iseconfig/main.xreport
Normal file
|
|
@ -0,0 +1,215 @@
|
|||
<?xml version='1.0' encoding='UTF-8'?>
|
||||
<report-views version="2.0" >
|
||||
<header>
|
||||
<DateModified>2013-02-18T14:32:38</DateModified>
|
||||
<ModuleName>main</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>C:/fpga/pong/iseconfig/main.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>C:/fpga/pong\</ImplementationReportsDirectory>
|
||||
<DateInitialized>2013-02-15T20:59:38</DateInitialized>
|
||||
<EnableMessageFiltering>false</EnableMessageFiltering>
|
||||
</header>
|
||||
<body>
|
||||
<viewgroup label="Design Overview" >
|
||||
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="main_summary.html" label="Summary" >
|
||||
<toc-item title="Design Overview" target="Design Overview" />
|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
|
||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
|
||||
</view>
|
||||
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="main_envsettings.html" label="System Settings" />
|
||||
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="main_map.xrpt" label="IOB Properties" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="main_map.xrpt" label="Control Set Information" />
|
||||
<view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="main_map.xrpt" label="Module Level Utilization" />
|
||||
<view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="main.ptwx" showConstraints="0" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="main_par.xrpt" label="Pinout Report" />
|
||||
<view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="main_par.xrpt" label="Clock Report" />
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="main.twx" label="Static Timing" />
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="main_html/fit/report.htm" label="CPLD Fitter Report" />
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="main_html/tim/report.htm" label="CPLD Timing Report" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Errors and Warnings" >
|
||||
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
|
||||
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
|
||||
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
|
||||
</viewgroup>
|
||||
<viewgroup label="XPS Reports" >
|
||||
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
|
||||
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
|
||||
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
|
||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="main.log" label="System Log File" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Errors and Warnings" >
|
||||
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
|
||||
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
|
||||
<view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
|
||||
<view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
|
||||
<view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
|
||||
<view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
|
||||
<view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
<view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
|
||||
<view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
|
||||
<view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
|
||||
</viewgroup>
|
||||
<viewgroup label="Detailed Reports" >
|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="main.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
|
||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
|
||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
|
||||
<toc-item title="HDL Analysis" target=" HDL Analysis " />
|
||||
<toc-item title="HDL Parsing" target=" HDL Parsing " />
|
||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
|
||||
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
|
||||
<toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
|
||||
<toc-item title="Advanced HDL Synthesis" target=" Advanced HDL Synthesis " searchDir="Backward" />
|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
<toc-item title="Partition Report" target=" Partition Report " />
|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
<toc-item title="Design Summary" target=" Design Summary " />
|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
|
||||
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
</view>
|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="main.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="main.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="main.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="main_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="main.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="main.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="main.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="main.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="main.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="main.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/main_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/main_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="main_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="main_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/main_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="main_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="main.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="main_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/main_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="main_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="main.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="main.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/main_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
95
iseconfig/pong.projectmgr
Normal file
95
iseconfig/pong.projectmgr
Normal file
|
|
@ -0,0 +1,95 @@
|
|||
<?xml version="1.0" encoding="utf-8"?>
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<!--It holds project specific layout data for the projectmgr plugin.-->
|
||||
<!--Copyright (c) 1995-2009 Xilinx, Inc. All rights reserved.-->
|
||||
<Project version="2" owner="projectmgr" name="pong" >
|
||||
<!--This is an ISE project configuration file.-->
|
||||
<ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>2</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>main - Behavioral (C:/fpga/pong/main.vhd)</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000123000000020000000000000000000000000200000064ffffffff000000810000000300000002000001230000000100000003000000000000000100000003</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
|
||||
<CurrentItem>main - Behavioral (C:/fpga/pong/main.vhd)</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Configure Target Device</ClosedNode>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>Synthesize - XST</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="File" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000126000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004200000001000000000000002400000001000000000000006600000001000000000000005a0000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView guiview="Library" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>work</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems/>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>work</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>Configure Target Device</ClosedNode>
|
||||
<ClosedNode>Design Utilities</ClosedNode>
|
||||
<ClosedNode>Implement Design</ClosedNode>
|
||||
<ClosedNode>Synthesize - XST</ClosedNode>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem>Generate Programming File</SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem>Generate Programming File</CurrentItem>
|
||||
</ItemView>
|
||||
<ItemView engineview="SynthesisOnly" sourcetype="DESUT_UCF" guiview="Process" >
|
||||
<ClosedNodes>
|
||||
<ClosedNodesVersion>1</ClosedNodesVersion>
|
||||
<ClosedNode>User Constraints</ClosedNode>
|
||||
</ClosedNodes>
|
||||
<SelectedItems>
|
||||
<SelectedItem></SelectedItem>
|
||||
</SelectedItems>
|
||||
<ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
|
||||
<ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
|
||||
<ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000</ViewHeaderState>
|
||||
<UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
|
||||
<CurrentItem></CurrentItem>
|
||||
</ItemView>
|
||||
<SourceProcessView>000000ff00000000000000020000011b0000011b01000000050100000002</SourceProcessView>
|
||||
<CurrentView>Implementation</CurrentView>
|
||||
</Project>
|
||||
94
main.bgn
Normal file
94
main.bgn
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
Release 14.1 - Bitgen P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
Loading device for application Rf_Device from file '3s250e.nph' in environment
|
||||
C:\Xilinx\14.1\ISE_DS\ISE\.
|
||||
"main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5
|
||||
Opened constraints file main.pcf.
|
||||
|
||||
Thu Feb 21 20:21:30 2013
|
||||
|
||||
C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No main.ncd
|
||||
|
||||
Summary of Bitgen Options:
|
||||
+----------------------+----------------------+
|
||||
| Option Name | Current Setting |
|
||||
+----------------------+----------------------+
|
||||
| Compress | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| Readback | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| CRC | Enable** |
|
||||
+----------------------+----------------------+
|
||||
| DebugBitstream | No** |
|
||||
+----------------------+----------------------+
|
||||
| ConfigRate | 1** |
|
||||
+----------------------+----------------------+
|
||||
| StartupClk | Cclk** |
|
||||
+----------------------+----------------------+
|
||||
| DCMShutdown | Disable** |
|
||||
+----------------------+----------------------+
|
||||
| DonePin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| ProgPin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| TckPin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| TdiPin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| TdoPin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| TmsPin | Pullup** |
|
||||
+----------------------+----------------------+
|
||||
| UnusedPin | Pulldown** |
|
||||
+----------------------+----------------------+
|
||||
| GWE_cycle | 6** |
|
||||
+----------------------+----------------------+
|
||||
| GTS_cycle | 5** |
|
||||
+----------------------+----------------------+
|
||||
| LCK_cycle | NoWait** |
|
||||
+----------------------+----------------------+
|
||||
| DONE_cycle | 4** |
|
||||
+----------------------+----------------------+
|
||||
| Persist | No* |
|
||||
+----------------------+----------------------+
|
||||
| DriveDone | No** |
|
||||
+----------------------+----------------------+
|
||||
| DonePipe | Yes |
|
||||
+----------------------+----------------------+
|
||||
| Security | None** |
|
||||
+----------------------+----------------------+
|
||||
| UserID | 0xFFFFFFFF** |
|
||||
+----------------------+----------------------+
|
||||
| MultiBootMode | No* |
|
||||
+----------------------+----------------------+
|
||||
| ActivateGclk | No* |
|
||||
+----------------------+----------------------+
|
||||
| ActiveReconfig | No* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask0 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask1 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialMask2 | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialGclk | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialLeft | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| PartialRight | (Not Specified)* |
|
||||
+----------------------+----------------------+
|
||||
| IEEE1532 | No* |
|
||||
+----------------------+----------------------+
|
||||
| Binary | No** |
|
||||
+----------------------+----------------------+
|
||||
* Default setting.
|
||||
** The specified setting matches the default setting.
|
||||
|
||||
There were 0 CONFIG constraint(s) processed from main.pcf.
|
||||
|
||||
|
||||
Running DRC.
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
Creating bit map...
|
||||
Saving bit stream in "main.bit".
|
||||
Bitstream generation is complete.
|
||||
BIN
main.bit
Normal file
BIN
main.bit
Normal file
Binary file not shown.
35
main.bld
Normal file
35
main.bld
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
Release 14.1 ngdbuild P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Command Line: C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle
|
||||
ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
|
||||
Reading NGO file "C:/fpga/pong/main.ngc" ...
|
||||
Gathering constraint information from source properties...
|
||||
Done.
|
||||
|
||||
Annotating constraints to design from ucf file "pins.ucf" ...
|
||||
Resolving constraint associations...
|
||||
Checking Constraint Associations...
|
||||
Done...
|
||||
|
||||
Checking expanded design ...
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
NGDBUILD Design Results Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
|
||||
Total memory usage is 129668 kilobytes
|
||||
|
||||
Writing NGD file "main.ngd" ...
|
||||
Total REAL time to NGDBUILD completion: 3 sec
|
||||
Total CPU time to NGDBUILD completion: 3 sec
|
||||
|
||||
Writing NGDBUILD log file "main.bld"...
|
||||
378
main.cmd_log
Normal file
378
main.cmd_log
Normal file
|
|
@ -0,0 +1,378 @@
|
|||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
|
||||
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
|
||||
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
bitgen -intstyle ise -f main.ut main.ncd
|
||||
8
main.drc
Normal file
8
main.drc
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
Release 14.1 Drc P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Thu Feb 21 20:21:30 2013
|
||||
|
||||
drc -z main.ncd main.pcf
|
||||
|
||||
DRC detected 0 errors and 0 warnings.
|
||||
1
main.lso
Normal file
1
main.lso
Normal file
|
|
@ -0,0 +1 @@
|
|||
work
|
||||
3
main.ncd
Normal file
3
main.ncd
Normal file
File diff suppressed because one or more lines are too long
3
main.ngc
Normal file
3
main.ngc
Normal file
File diff suppressed because one or more lines are too long
3
main.ngd
Normal file
3
main.ngd
Normal file
File diff suppressed because one or more lines are too long
3
main.ngr
Normal file
3
main.ngr
Normal file
File diff suppressed because one or more lines are too long
162
main.pad
Normal file
162
main.pad
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
Release 14.1 - par P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Thu Feb 21 20:21:23 2013
|
||||
|
||||
|
||||
# NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
INPUT FILE: main_map.ncd
|
||||
OUTPUT FILE: main.pad
|
||||
PART TYPE: xc3s250e
|
||||
SPEED GRADE: -5
|
||||
PACKAGE: cp132
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
|
||||
A1|||PROG_B||||||||||||
|
||||
A2|||TDI||||||||||||
|
||||
A3||DIFFM|IO_L11P_0|UNUSED||0|||||||||
|
||||
A4|||GND||||||||||||
|
||||
A5|||VCCAUX||||||||2.5||||
|
||||
A6|||VCCO_0|||0|||||any******||||
|
||||
A7||DIFFM|IO_L07P_0/GCLK10|UNUSED||0|||||||||
|
||||
A8|||GND||||||||||||
|
||||
A9||DIFFS|IO_L05N_0/GCLK7|UNUSED||0|||||||||
|
||||
A10||DIFFM|IO_L04P_0/GCLK4|UNUSED||0|||||||||
|
||||
A11|||VCCINT||||||||1.2||||
|
||||
A12||DIFFS|IO_L02N_0|UNUSED||0|||||||||
|
||||
A13||DIFFM|IO_L01P_0|UNUSED||0|||||||||
|
||||
A14|||TDO||||||||||||
|
||||
B1||DIFFS|IO_L01N_3|UNUSED||3|||||||||
|
||||
B2||DIFFM|IO_L01P_3|UNUSED||3|||||||||
|
||||
B3||DIFFS|IO_L11N_0/HSWAP|UNUSED||0|||||||||
|
||||
B4||DIFFM|IO_L10P_0|UNUSED||0|||||||||
|
||||
B5||DIFFM|IO_L09P_0|UNUSED||0|||||||||
|
||||
B6||DIFFM|IO_L08P_0|UNUSED||0|||||||||
|
||||
B7||DIFFS|IO_L07N_0/GCLK11|UNUSED||0|||||||||
|
||||
B8||DIFFMI|IP_L06P_0/GCLK8|UNUSED||0|||||||||
|
||||
B9||DIFFM|IO_L05P_0/GCLK6|UNUSED||0|||||||||
|
||||
B10|||VCCO_0|||0|||||any******||||
|
||||
B11||DIFFS|IO_L03N_0/VREF_0|UNUSED||0|||||||||
|
||||
B12||DIFFM|IO_L02P_0|UNUSED||0|||||||||
|
||||
B13|||TCK||||||||||||
|
||||
B14|||TMS||||||||||||
|
||||
C1|||GND||||||||||||
|
||||
C2||DIFFS|IO_L02N_3|UNUSED||3|||||||||
|
||||
C3||DIFFM|IO_L02P_3|UNUSED||3|||||||||
|
||||
C4||DIFFS|IO_L10N_0|UNUSED||0|||||||||
|
||||
C5||DIFFS|IO_L09N_0|UNUSED||0|||||||||
|
||||
C6||DIFFS|IO_L08N_0/VREF_0|UNUSED||0|||||||||
|
||||
C7|||GND||||||||||||
|
||||
C8||DIFFSI|IP_L06N_0/GCLK9|UNUSED||0|||||||||
|
||||
C9||DIFFS|IO_L04N_0/GCLK5|UNUSED||0|||||||||
|
||||
C10|||GND||||||||||||
|
||||
C11||DIFFM|IO_L03P_0|UNUSED||0|||||||||
|
||||
C12||DIFFS|IO_L01N_0|UNUSED||0|||||||||
|
||||
C13||DIFFS|IO_L10N_1/LDC2|UNUSED||1|||||||||
|
||||
C14|RGB<5>|IOB|IO_L10P_1/LDC1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
D1||DIFFS|IO_L03N_3|UNUSED||3|||||||||
|
||||
D2||DIFFM|IO_L03P_3|UNUSED||3|||||||||
|
||||
D3|||VCCINT||||||||1.2||||
|
||||
D12||DIFFS|IO_L09N_1/LDC0|UNUSED||1|||||||||
|
||||
D13|RGB<6>|IOB|IO_L09P_1/HDC|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
D14|||NC||||||||||||
|
||||
E1|||VCCO_3|||3|||||2.50||||
|
||||
E2||IBUF|IP/VREF_3|UNUSED||3|||||||||
|
||||
E3|||GND||||||||||||
|
||||
E12|||VCCAUX||||||||2.5||||
|
||||
E13|||VCCO_1|||1|||||3.30||||
|
||||
E14|||GND||||||||||||
|
||||
F1||DIFFM|IO_L05P_3/LHCLK2|UNUSED||3|||||||||
|
||||
F2||DIFFS|IO_L04N_3/LHCLK1|UNUSED||3|||||||||
|
||||
F3||DIFFM|IO_L04P_3/LHCLK0|UNUSED||3|||||||||
|
||||
F12||DIFFS|IO/A0|UNUSED||1|||||||||
|
||||
F13|RGB<7>|IOB|IO_L08N_1/A1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
F14|RGB<2>|IOB|IO_L08P_1/A2|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
G1|LED<7>|IOB|IO_L05N_3/LHCLK3/IRDY2|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
G2|||GND||||||||||||
|
||||
G3||DIFFM|IO_L06P_3/LHCLK4/TRDY2|UNUSED||3|||||||||
|
||||
G12||IBUF|IP/VREF_1|UNUSED||1|||||||||
|
||||
G13|RGB<3>|IOB|IO_L07N_1/A3/RHCLK7|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
G14|RGB<4>|IOB|IO_L07P_1/A4/RHCLK6|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
H1||DIFFS|IO_L06N_3/LHCLK5|UNUSED||3|||||||||
|
||||
H2||DIFFM|IO_L07P_3/LHCLK6|UNUSED||3|||||||||
|
||||
H3||DIFFS|IO_L07N_3/LHCLK7|UNUSED||3|||||||||
|
||||
H12||DIFFS|IO_L06N_1/A5/RHCLK5|UNUSED||1|||||||||
|
||||
H13|RGB<0>|IOB|IO_L06P_1/A6/RHCLK4/IRDY1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
H14|||GND||||||||||||
|
||||
J1|||GND||||||||||||
|
||||
J2|||VCCO_3|||3|||||2.50||||
|
||||
J3||DIFFS|IO|UNUSED||3|||||||||
|
||||
J12||DIFFS|IO_L04N_1/A9/RHCLK1|UNUSED||1|||||||||
|
||||
J13|RGB<1>|IOB|IO_L05P_1/A8/RHCLK2|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
J14|HS|IOB|IO_L05N_1/A7/RHCLK3/TRDY1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
K1|||VCCAUX||||||||2.5||||
|
||||
K2|||NC||||||||||||
|
||||
K3||IOB|IO/VREF_3|UNUSED||3|||||||||
|
||||
K12|||GND||||||||||||
|
||||
K13|VS|IOB|IO/VREF_1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE|
|
||||
K14||DIFFM|IO_L04P_1/A10/RHCLK0|UNUSED||1|||||||||
|
||||
L1||DIFFM|IO_L08P_3|UNUSED||3|||||||||
|
||||
L2||DIFFS|IO_L08N_3|UNUSED||3|||||||||
|
||||
L3||DIFFM|IO_L09P_3|UNUSED||3|||||||||
|
||||
L12|||VCCINT||||||||1.2||||
|
||||
L13||DIFFM|IO_L03P_1/A12|UNUSED||1|||||||||
|
||||
L14||DIFFS|IO_L03N_1/A11|UNUSED||1|||||||||
|
||||
M1||DIFFS|IO_L09N_3|UNUSED||3|||||||||
|
||||
M2||DIFFM|IO_L01P_2/CSO_B|UNUSED||2|||||||||
|
||||
M3|||GND||||||||||||
|
||||
M4||DIFFM|IO_L03P_2/D7/GCLK12|UNUSED||2|||||||||
|
||||
M5|LED<0>|IOB|IO_L04P_2/D4/GCLK14|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
M6|CLK|IBUF|IP_L05P_2/RDWR_B/GCLK0|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE|
|
||||
M7|||GND||||||||||||
|
||||
M8|||VCCO_2|||2|||||2.50||||
|
||||
M9||DIFFS|IO_L08N_2/A22|UNUSED||2|||||||||
|
||||
M10||DIFFS|IO_L09N_2/A20|UNUSED||2|||||||||
|
||||
M11|LED<1>|IOB|IO_L10N_2/VS1/A18|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
M12||DIFFM|IO_L02P_1/A14|UNUSED||1|||||||||
|
||||
M13||DIFFS|IO_L02N_1/A13|UNUSED||1|||||||||
|
||||
M14|||VCCO_1|||1|||||3.30||||
|
||||
N1||DIFFS|IO_L01N_2/INIT_B|UNUSED||2|||||||||
|
||||
N2||DIFFS|IO_L02N_2/MOSI/CSI_B|UNUSED||2|||||||||
|
||||
N3||DIFFSI|IP/VREF_2|UNUSED||2|||||||||
|
||||
N4|LED<5>|IOB|IO_L03N_2/D6/GCLK13|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
N5|LED<4>|IOB|IO_L04N_2/D3/GCLK15|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
N6||DIFFSI|IP_L05N_2/M2/GCLK1|UNUSED||2|||||||||
|
||||
N7||IOB|IO/M1|UNUSED||2|||||||||
|
||||
N8||DIFFS|IO_L07N_2/DIN/D0|UNUSED||2|||||||||
|
||||
N9||DIFFM|IO_L08P_2/A23|UNUSED||2|||||||||
|
||||
N10||DIFFM|IO_L09P_2/A21|UNUSED||2|||||||||
|
||||
N11||DIFFM|IO_L10P_2/VS2/A19|UNUSED||2|||||||||
|
||||
N12||DIFFS|IO_L11N_2/CCLK|UNUSED||2|||||||||
|
||||
N13||DIFFM|IO_L01P_1/A16|UNUSED||1|||||||||
|
||||
N14||DIFFS|IO_L01N_1/A15|UNUSED||1|||||||||
|
||||
P1||DIFFM|IO_L02P_2/DOUT/BUSY|UNUSED||2|||||||||
|
||||
P2|||VCCINT||||||||1.2||||
|
||||
P3|||VCCO_2|||2|||||2.50||||
|
||||
P4|LED<6>|IOB|IO/D5|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P5|||GND||||||||||||
|
||||
P6|LED<3>|IOB|IO_L06P_2/D2/GCLK2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P7|LED<2>|IOB|IO_L06N_2/D1/GCLK3|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE|
|
||||
P8||DIFFM|IO_L07P_2/M0|UNUSED||2|||||||||
|
||||
P9|||VCCAUX||||||||2.5||||
|
||||
P10|||GND||||||||||||
|
||||
P11||IOB|IO/VREF_2|UNUSED||2|||||||||
|
||||
P12||DIFFM|IO_L11P_2/VS0/A17|UNUSED||2|||||||||
|
||||
P13|||DONE||||||||||||
|
||||
P14|||GND||||||||||||
|
||||
|
||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
209
main.par
Normal file
209
main.par
Normal file
|
|
@ -0,0 +1,209 @@
|
|||
Release 14.1 par P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
ALECO-PC:: Thu Feb 21 20:21:13 2013
|
||||
|
||||
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
|
||||
|
||||
|
||||
Constraints file: main.pcf.
|
||||
Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx\14.1\ISE_DS\ISE\.
|
||||
"main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5
|
||||
|
||||
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
|
||||
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
|
||||
|
||||
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
|
||||
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
|
||||
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
|
||||
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
|
||||
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
|
||||
|
||||
Device speed data version: "PRODUCTION 1.27 2012-04-23".
|
||||
|
||||
|
||||
Design Summary Report:
|
||||
|
||||
Number of External IOBs 19 out of 92 20%
|
||||
|
||||
Number of External Input IOBs 1
|
||||
|
||||
Number of External Input IBUFs 1
|
||||
Number of LOCed External Input IBUFs 1 out of 1 100%
|
||||
|
||||
|
||||
Number of External Output IOBs 18
|
||||
|
||||
Number of External Output IOBs 18
|
||||
Number of LOCed External Output IOBs 18 out of 18 100%
|
||||
|
||||
|
||||
Number of External Bidir IOBs 0
|
||||
|
||||
|
||||
Number of BUFGMUXs 1 out of 24 4%
|
||||
Number of Slices 52 out of 2448 2%
|
||||
Number of SLICEMs 0 out of 1224 0%
|
||||
|
||||
|
||||
|
||||
Overall effort level (-ol): High
|
||||
Placer effort level (-pl): High
|
||||
Placer cost table entry (-t): 1
|
||||
Router effort level (-rl): High
|
||||
|
||||
Starting initial Timing Analysis. REAL time: 1 secs
|
||||
Finished initial Timing Analysis. REAL time: 1 secs
|
||||
|
||||
|
||||
Starting Placer
|
||||
Total REAL time at the beginning of Placer: 1 secs
|
||||
Total CPU time at the beginning of Placer: 1 secs
|
||||
|
||||
Phase 1.1 Initial Placement Analysis
|
||||
Phase 1.1 Initial Placement Analysis (Checksum:130c5420) REAL time: 1 secs
|
||||
|
||||
Phase 2.7 Design Feasibility Check
|
||||
Phase 2.7 Design Feasibility Check (Checksum:130c5420) REAL time: 1 secs
|
||||
|
||||
Phase 3.31 Local Placement Optimization
|
||||
Phase 3.31 Local Placement Optimization (Checksum:130c5420) REAL time: 1 secs
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement
|
||||
|
||||
Phase 4.2 Initial Clock and IO Placement (Checksum:2104b6b4) REAL time: 1 secs
|
||||
|
||||
Phase 5.30 Global Clock Region Assignment
|
||||
Phase 5.30 Global Clock Region Assignment (Checksum:2104b6b4) REAL time: 1 secs
|
||||
|
||||
Phase 6.36 Local Placement Optimization
|
||||
Phase 6.36 Local Placement Optimization (Checksum:2104b6b4) REAL time: 1 secs
|
||||
|
||||
Phase 7.8 Global Placement
|
||||
.........
|
||||
..
|
||||
Phase 7.8 Global Placement (Checksum:5dd09b6d) REAL time: 4 secs
|
||||
|
||||
Phase 8.5 Local Placement Optimization
|
||||
Phase 8.5 Local Placement Optimization (Checksum:5dd09b6d) REAL time: 4 secs
|
||||
|
||||
Phase 9.18 Placement Optimization
|
||||
Phase 9.18 Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs
|
||||
|
||||
Phase 10.5 Local Placement Optimization
|
||||
Phase 10.5 Local Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs
|
||||
|
||||
Total REAL time to Placer completion: 4 secs
|
||||
Total CPU time to Placer completion: 4 secs
|
||||
Writing design to file main.ncd
|
||||
|
||||
|
||||
|
||||
Starting Router
|
||||
|
||||
|
||||
Phase 1 : 319 unrouted; REAL time: 7 secs
|
||||
|
||||
Phase 2 : 284 unrouted; REAL time: 7 secs
|
||||
|
||||
Phase 3 : 35 unrouted; REAL time: 7 secs
|
||||
|
||||
Phase 4 : 69 unrouted; (Par is working to improve performance) REAL time: 7 secs
|
||||
|
||||
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
|
||||
|
||||
Updating file: main.ncd with current fully routed design.
|
||||
|
||||
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs
|
||||
|
||||
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
|
||||
|
||||
Updating file: main.ncd with current fully routed design.
|
||||
|
||||
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
|
||||
|
||||
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
|
||||
|
||||
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
|
||||
|
||||
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
|
||||
|
||||
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
|
||||
WARNING:Route:455 - CLK Net:VGADriver/W may have excessive skew because
|
||||
2 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
|
||||
|
||||
Total REAL time to Router completion: 10 secs
|
||||
Total CPU time to Router completion: 9 secs
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Generating "PAR" statistics.
|
||||
|
||||
**************************
|
||||
Generating Clock Report
|
||||
**************************
|
||||
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| CLK_BUFGP | BUFGMUX_X2Y1| No | 25 | 0.037 | 0.098 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
| VGADriver/W | Local| | 2 | 0.000 | 1.219 |
|
||||
+---------------------+--------------+------+------+------------+-------------+
|
||||
|
||||
* Net Skew is the difference between the minimum and maximum routing
|
||||
only delays for the net. Note this is different from Clock Skew which
|
||||
is reported in TRCE timing report. Clock Skew is the difference between
|
||||
the minimum and maximum path delays which includes logic delays.
|
||||
|
||||
* The fanout is the number of component pins not the individual BEL loads,
|
||||
for example SLICE loads not FF loads.
|
||||
|
||||
Timing Score: 0 (Setup: 0, Hold: 0)
|
||||
|
||||
Asterisk (*) preceding a constraint indicates it was not met.
|
||||
This may be due to a setup or hold violation.
|
||||
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Constraint | Check | Worst Case | Best Case | Timing | Timing
|
||||
| | Slack | Achievable | Errors | Score
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
Autotimespec constraint for clock net CLK | SETUP | N/A| 5.493ns| N/A| 0
|
||||
_BUFGP | HOLD | 1.410ns| | 0| 0
|
||||
----------------------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
All constraints were met.
|
||||
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
|
||||
constraint is not analyzed due to the following: No paths covered by this
|
||||
constraint; Other constraints intersect with this constraint; or This
|
||||
constraint was disabled by a Path Tracing Control. Please run the Timespec
|
||||
Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
|
||||
|
||||
|
||||
Generating Pad Report.
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
Total REAL time to PAR completion: 10 secs
|
||||
Total CPU time to PAR completion: 9 secs
|
||||
|
||||
Peak Memory Usage: 228 MB
|
||||
|
||||
Placement: Completed - No errors found.
|
||||
Routing: Completed - No errors found.
|
||||
|
||||
Number of error messages: 0
|
||||
Number of warning messages: 1
|
||||
Number of info messages: 1
|
||||
|
||||
Writing design to file main.ncd
|
||||
|
||||
|
||||
|
||||
PAR done!
|
||||
27
main.pcf
Normal file
27
main.pcf
Normal file
|
|
@ -0,0 +1,27 @@
|
|||
//! **************************************************************************
|
||||
// Written by: Map P.15xf on Thu Feb 21 20:21:10 2013
|
||||
//! **************************************************************************
|
||||
|
||||
SCHEMATIC START;
|
||||
COMP "HS" LOCATE = SITE "J14" LEVEL 1;
|
||||
COMP "LED<0>" LOCATE = SITE "M5" LEVEL 1;
|
||||
COMP "LED<1>" LOCATE = SITE "M11" LEVEL 1;
|
||||
COMP "LED<2>" LOCATE = SITE "P7" LEVEL 1;
|
||||
COMP "RGB<0>" LOCATE = SITE "H13" LEVEL 1;
|
||||
COMP "LED<3>" LOCATE = SITE "P6" LEVEL 1;
|
||||
COMP "RGB<1>" LOCATE = SITE "J13" LEVEL 1;
|
||||
COMP "LED<4>" LOCATE = SITE "N5" LEVEL 1;
|
||||
COMP "RGB<2>" LOCATE = SITE "F14" LEVEL 1;
|
||||
COMP "LED<5>" LOCATE = SITE "N4" LEVEL 1;
|
||||
COMP "RGB<3>" LOCATE = SITE "G13" LEVEL 1;
|
||||
COMP "LED<6>" LOCATE = SITE "P4" LEVEL 1;
|
||||
COMP "RGB<4>" LOCATE = SITE "G14" LEVEL 1;
|
||||
COMP "LED<7>" LOCATE = SITE "G1" LEVEL 1;
|
||||
COMP "RGB<5>" LOCATE = SITE "C14" LEVEL 1;
|
||||
COMP "RGB<6>" LOCATE = SITE "D13" LEVEL 1;
|
||||
COMP "VS" LOCATE = SITE "K13" LEVEL 1;
|
||||
COMP "RGB<7>" LOCATE = SITE "F13" LEVEL 1;
|
||||
COMP "CLK" LOCATE = SITE "M6" LEVEL 1;
|
||||
NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
|
||||
SCHEMATIC END;
|
||||
|
||||
2
main.prj
Normal file
2
main.prj
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
vhdl work "vga.vhd"
|
||||
vhdl work "main.vhd"
|
||||
332
main.ptwx
Normal file
332
main.ptwx
Normal file
|
|
@ -0,0 +1,332 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK_BUFGP</twConstName><twConstData type="SETUP" best="5.493" units="ns" score="0"/><twConstData type="HOLD" slack="1.410" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="21">0</twUnmetConstCnt><twInfo anchorID="22">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>
|
||||
0
main.stx
Normal file
0
main.stx
Normal file
423
main.syr
Normal file
423
main.syr
Normal file
|
|
@ -0,0 +1,423 @@
|
|||
Release 14.1 - xst P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
--> Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.11 secs
|
||||
|
||||
--> Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.11 secs
|
||||
|
||||
--> Reading design: main.prj
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) Design Hierarchy Analysis
|
||||
4) HDL Analysis
|
||||
5) HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Advanced HDL Synthesis
|
||||
6.1) Advanced HDL Synthesis Report
|
||||
7) Low Level Synthesis
|
||||
8) Partition Report
|
||||
9) Final Report
|
||||
9.1) Device utilization summary
|
||||
9.2) Partition Resource Summary
|
||||
9.3) TIMING REPORT
|
||||
|
||||
|
||||
=========================================================================
|
||||
* Synthesis Options Summary *
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "main.prj"
|
||||
Input Format : mixed
|
||||
Ignore Synthesis Constraint File : NO
|
||||
|
||||
---- Target Parameters
|
||||
Output File Name : "main"
|
||||
Output Format : NGC
|
||||
Target Device : xc3s250e-5-cp132
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : main
|
||||
Automatic FSM Extraction : YES
|
||||
FSM Encoding Algorithm : Auto
|
||||
Safe Implementation : No
|
||||
FSM Style : LUT
|
||||
RAM Extraction : Yes
|
||||
RAM Style : Auto
|
||||
ROM Extraction : Yes
|
||||
Mux Style : Auto
|
||||
Decoder Extraction : YES
|
||||
Priority Encoder Extraction : Yes
|
||||
Shift Register Extraction : YES
|
||||
Logical Shifter Extraction : YES
|
||||
XOR Collapsing : YES
|
||||
ROM Style : Auto
|
||||
Mux Extraction : Yes
|
||||
Resource Sharing : YES
|
||||
Asynchronous To Synchronous : NO
|
||||
Multiplier Style : Auto
|
||||
Automatic Register Balancing : No
|
||||
|
||||
---- Target Options
|
||||
Add IO Buffers : YES
|
||||
Global Maximum Fanout : 100000
|
||||
Add Generic Clock Buffer(BUFG) : 24
|
||||
Register Duplication : YES
|
||||
Slice Packing : YES
|
||||
Optimize Instantiated Primitives : NO
|
||||
Use Clock Enable : Yes
|
||||
Use Synchronous Set : Yes
|
||||
Use Synchronous Reset : Yes
|
||||
Pack IO Registers into IOBs : Auto
|
||||
Equivalent register Removal : YES
|
||||
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Keep Hierarchy : No
|
||||
Netlist Hierarchy : As_Optimized
|
||||
RTL Output : Yes
|
||||
Global Optimization : AllClockNets
|
||||
Read Cores : YES
|
||||
Write Timing Constraints : NO
|
||||
Cross Clock Analysis : NO
|
||||
Hierarchy Separator : /
|
||||
Bus Delimiter : <>
|
||||
Case Specifier : Maintain
|
||||
Slice Utilization Ratio : 100
|
||||
BRAM Utilization Ratio : 100
|
||||
Verilog 2001 : YES
|
||||
Auto BRAM Packing : NO
|
||||
Slice Utilization Ratio Delta : 5
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
=========================================================================
|
||||
Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work.
|
||||
Entity <vga> compiled.
|
||||
Entity <vga> (Architecture <behavioral>) compiled.
|
||||
Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work.
|
||||
Architecture behavioral of Entity main is up to date.
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
|
||||
|
||||
Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>).
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <main> in library <work> (Architecture <behavioral>).
|
||||
WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
|
||||
<w>, <x>, <y>
|
||||
Entity <main> analyzed. Unit <main> generated.
|
||||
|
||||
Analyzing Entity <vga> in library <work> (Architecture <behavioral>).
|
||||
Entity <vga> analyzed. Unit <vga> generated.
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <vga>.
|
||||
Related source file is "C:/fpga/pong/vga.vhd".
|
||||
WARNING:Xst:1305 - Output <LED> is never assigned. Tied to value 00000000.
|
||||
Found 1-bit register for signal <HS>.
|
||||
Found 1-bit register for signal <W>.
|
||||
Found 10-bit register for signal <X>.
|
||||
Found 10-bit register for signal <Y>.
|
||||
Found 1-bit register for signal <VS>.
|
||||
Found 8-bit register for signal <RGB>.
|
||||
Found 10-bit up counter for signal <horiz>.
|
||||
Found 11-bit comparator greater for signal <HS$cmp_gt0000> created at line 44.
|
||||
Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 44.
|
||||
Found 10-bit up counter for signal <vert>.
|
||||
Found 11-bit comparator greater for signal <VS$cmp_gt0000> created at line 50.
|
||||
Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 50.
|
||||
Found 11-bit comparator greatequal for signal <W$cmp_ge0000> created at line 32.
|
||||
Found 11-bit comparator greatequal for signal <W$cmp_ge0001> created at line 32.
|
||||
Found 11-bit comparator less for signal <W$cmp_lt0000> created at line 32.
|
||||
Found 11-bit comparator less for signal <W$cmp_lt0001> created at line 32.
|
||||
Found 10-bit adder for signal <X$add0000> created at line 37.
|
||||
Found 10-bit subtractor for signal <X$addsub0000> created at line 37.
|
||||
Found 10-bit adder for signal <Y$add0000> created at line 38.
|
||||
Found 10-bit subtractor for signal <Y$addsub0000> created at line 38.
|
||||
Summary:
|
||||
inferred 2 Counter(s).
|
||||
inferred 31 D-type flip-flop(s).
|
||||
inferred 4 Adder/Subtractor(s).
|
||||
inferred 8 Comparator(s).
|
||||
Unit <vga> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <main>.
|
||||
Related source file is "C:/fpga/pong/main.vhd".
|
||||
WARNING:Xst:737 - Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
|
||||
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0000> created at line 59.
|
||||
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0001> created at line 59.
|
||||
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0000> created at line 59.
|
||||
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0001> created at line 59.
|
||||
Summary:
|
||||
inferred 4 Comparator(s).
|
||||
Unit <main> synthesized.
|
||||
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 4
|
||||
10-bit adder : 2
|
||||
10-bit subtractor : 2
|
||||
# Counters : 2
|
||||
10-bit up counter : 2
|
||||
# Registers : 6
|
||||
1-bit register : 3
|
||||
10-bit register : 2
|
||||
8-bit register : 1
|
||||
# Latches : 1
|
||||
8-bit latch : 1
|
||||
# Comparators : 12
|
||||
11-bit comparator greatequal : 4
|
||||
11-bit comparator greater : 2
|
||||
11-bit comparator less : 4
|
||||
11-bit comparator lessequal : 2
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Advanced HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
|
||||
=========================================================================
|
||||
Advanced HDL Synthesis Report
|
||||
|
||||
Macro Statistics
|
||||
# Adders/Subtractors : 4
|
||||
10-bit adder : 2
|
||||
10-bit subtractor : 2
|
||||
# Counters : 2
|
||||
10-bit up counter : 2
|
||||
# Registers : 31
|
||||
Flip-Flops : 31
|
||||
# Latches : 1
|
||||
8-bit latch : 1
|
||||
# Comparators : 12
|
||||
11-bit comparator greatequal : 4
|
||||
11-bit comparator greater : 2
|
||||
11-bit comparator less : 4
|
||||
11-bit comparator lessequal : 2
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Low Level Synthesis *
|
||||
=========================================================================
|
||||
INFO:Xst:2261 - The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 4 FFs/Latches, which will be removed : <6> <5> <1> <0>
|
||||
INFO:Xst:2261 - The FF/Latch <4> in Unit <LPM_LATCH_1> is equivalent to the following 2 FFs/Latches, which will be removed : <3> <2>
|
||||
|
||||
Optimizing unit <main> ...
|
||||
|
||||
Optimizing unit <vga> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_4> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <VGADriver/RGB_3> <VGADriver/RGB_2>
|
||||
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 4 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_1> <VGADriver/RGB_0>
|
||||
Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 2.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
=========================================================================
|
||||
Final Register Report
|
||||
|
||||
Macro Statistics
|
||||
# Registers : 45
|
||||
Flip-Flops : 45
|
||||
|
||||
=========================================================================
|
||||
|
||||
=========================================================================
|
||||
* Partition Report *
|
||||
=========================================================================
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : main.ngr
|
||||
Top Level Output File Name : main
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : No
|
||||
|
||||
Design Statistics
|
||||
# IOs : 19
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 189
|
||||
# GND : 1
|
||||
# INV : 11
|
||||
# LUT1 : 33
|
||||
# LUT2 : 1
|
||||
# LUT2_L : 1
|
||||
# LUT3 : 6
|
||||
# LUT3_L : 3
|
||||
# LUT4 : 29
|
||||
# LUT4_D : 1
|
||||
# LUT4_L : 4
|
||||
# MUXCY : 45
|
||||
# MUXF5 : 3
|
||||
# VCC : 1
|
||||
# XORCY : 50
|
||||
# FlipFlops/Latches : 47
|
||||
# FD : 1
|
||||
# FDE : 20
|
||||
# FDR : 13
|
||||
# FDRE : 10
|
||||
# FDS : 1
|
||||
# LD : 2
|
||||
# Clock Buffers : 1
|
||||
# BUFGP : 1
|
||||
# IO Buffers : 18
|
||||
# OBUF : 18
|
||||
=========================================================================
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 3s250ecp132-5
|
||||
|
||||
Number of Slices: 50 out of 2448 2%
|
||||
Number of Slice Flip Flops: 47 out of 4896 0%
|
||||
Number of 4 input LUTs: 89 out of 4896 1%
|
||||
Number of IOs: 19
|
||||
Number of bonded IOBs: 19 out of 92 20%
|
||||
Number of GCLKs: 1 out of 24 4%
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
---------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
---------------------------
|
||||
|
||||
|
||||
=========================================================================
|
||||
TIMING REPORT
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
GENERATED AFTER PLACE-and-ROUTE.
|
||||
|
||||
Clock Information:
|
||||
------------------
|
||||
-----------------------------------+------------------------+-------+
|
||||
Clock Signal | Clock buffer(FF name) | Load |
|
||||
-----------------------------------+------------------------+-------+
|
||||
VGADriver/W | NONE(inrgb_4) | 2 |
|
||||
CLK | BUFGP | 45 |
|
||||
-----------------------------------+------------------------+-------+
|
||||
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
|
||||
|
||||
Asynchronous Control Signals Information:
|
||||
----------------------------------------
|
||||
No asynchronous control signals found in this design
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -5
|
||||
|
||||
Minimum period: 5.905ns (Maximum Frequency: 169.349MHz)
|
||||
Minimum input arrival time before clock: No path found
|
||||
Maximum output required time after clock: 4.221ns
|
||||
Maximum combinational path delay: No path found
|
||||
|
||||
Timing Detail:
|
||||
--------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default period analysis for Clock 'CLK'
|
||||
Clock period: 5.905ns (frequency: 169.349MHz)
|
||||
Total number of paths / destination ports: 1505 / 95
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 5.905ns (Levels of Logic = 4)
|
||||
Source: VGADriver/vert_6 (FF)
|
||||
Destination: VGADriver/Y_9 (FF)
|
||||
Source Clock: CLK rising
|
||||
Destination Clock: CLK rising
|
||||
|
||||
Data Path: VGADriver/vert_6 to VGADriver/Y_9
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDRE:C->Q 4 0.514 0.651 VGADriver/vert_6 (VGADriver/vert_6)
|
||||
LUT2_L:I0->LO 1 0.612 0.103 VGADriver/vert_cmp_eq00001_SW0 (VGADriver/X_and000093)
|
||||
LUT4:I3->O 3 0.612 0.454 VGADriver/vert_cmp_eq00001 (VGADriver/N7)
|
||||
LUT4_D:I3->O 4 0.612 0.502 VGADriver/X_and0000136 (VGADriver/X_and0000136)
|
||||
LUT4:I3->O 10 0.612 0.750 VGADriver/X_and0000151_2 (VGADriver/X_and0000151_1)
|
||||
FDE:CE 0.483 VGADriver/Y_0
|
||||
----------------------------------------
|
||||
Total 5.905ns (3.445ns logic, 2.460ns route)
|
||||
(58.3% logic, 41.7% route)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
|
||||
Total number of paths / destination ports: 10 / 10
|
||||
-------------------------------------------------------------------------
|
||||
Offset: 4.221ns (Levels of Logic = 1)
|
||||
Source: VGADriver/RGB_7 (FF)
|
||||
Destination: RGB<7> (PAD)
|
||||
Source Clock: CLK rising
|
||||
|
||||
Data Path: VGADriver/RGB_7 to RGB<7>
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
FDS:C->Q 5 0.514 0.538 VGADriver/RGB_7 (VGADriver/RGB_7)
|
||||
OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>)
|
||||
----------------------------------------
|
||||
Total 4.221ns (3.683ns logic, 0.538ns route)
|
||||
(87.3% logic, 12.7% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 6.00 secs
|
||||
Total CPU time to Xst completion: 5.42 secs
|
||||
|
||||
-->
|
||||
|
||||
Total memory usage is 217424 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 3 ( 0 filtered)
|
||||
Number of infos : 5 ( 0 filtered)
|
||||
|
||||
78
main.twr
Normal file
78
main.twr
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
--------------------------------------------------------------------------------
|
||||
Release 14.1 Trace (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n
|
||||
3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
|
||||
Design file: main.ncd
|
||||
Physical constraint file: main.pcf
|
||||
Device,package,speed: xc3s250e,cp132,-5 (PRODUCTION 1.27 2012-04-23)
|
||||
Report level: verbose report
|
||||
|
||||
Environment Variable Effect
|
||||
-------------------- ------
|
||||
NONE No environment variables were set
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
|
||||
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
|
||||
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
|
||||
option. All paths that are not constrained will be reported in the
|
||||
unconstrained paths section(s) of the report.
|
||||
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
|
||||
a 50 Ohm transmission line loading model. For the details of this model,
|
||||
and for more information on accounting for different loading conditions,
|
||||
please see the device datasheet.
|
||||
INFO:Timing:3390 - This architecture does not support a default System Jitter
|
||||
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
|
||||
Uncertainty calculation.
|
||||
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
|
||||
'Phase Error' calculations, these terms will be zero in the Clock
|
||||
Uncertainty calculation. Please make appropriate modification to
|
||||
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
|
||||
Error.
|
||||
|
||||
|
||||
|
||||
Data Sheet report:
|
||||
-----------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
Clock CLK to Pad
|
||||
------------+------------+------------------+--------+
|
||||
| clk (edge) | | Clock |
|
||||
Destination | to PAD |Internal Clock(s) | Phase |
|
||||
------------+------------+------------------+--------+
|
||||
HS | 6.320(R)|CLK_BUFGP | 0.000|
|
||||
RGB<0> | 7.061(R)|CLK_BUFGP | 0.000|
|
||||
RGB<1> | 7.052(R)|CLK_BUFGP | 0.000|
|
||||
RGB<2> | 7.348(R)|CLK_BUFGP | 0.000|
|
||||
RGB<3> | 7.565(R)|CLK_BUFGP | 0.000|
|
||||
RGB<4> | 7.538(R)|CLK_BUFGP | 0.000|
|
||||
RGB<5> | 8.606(R)|CLK_BUFGP | 0.000|
|
||||
RGB<6> | 8.389(R)|CLK_BUFGP | 0.000|
|
||||
RGB<7> | 7.981(R)|CLK_BUFGP | 0.000|
|
||||
VS | 6.627(R)|CLK_BUFGP | 0.000|
|
||||
------------+------------+------------------+--------+
|
||||
|
||||
Clock to Setup on destination clock CLK
|
||||
---------------+---------+---------+---------+---------+
|
||||
| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
|
||||
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
|
||||
---------------+---------+---------+---------+---------+
|
||||
CLK | 5.493| | | |
|
||||
---------------+---------+---------+---------+---------+
|
||||
|
||||
|
||||
Analysis completed Thu Feb 21 20:21:26 2013
|
||||
--------------------------------------------------------------------------------
|
||||
|
||||
Trace Settings:
|
||||
-------------------------
|
||||
Trace Settings
|
||||
|
||||
Peak Memory Usage: 129 MB
|
||||
|
||||
|
||||
|
||||
338
main.twx
Normal file
338
main.twx
Normal file
|
|
@ -0,0 +1,338 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE twReport [
|
||||
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
|
||||
twDebug*, twFoot?, twClientInfo?)>
|
||||
<!ATTLIST twReport version CDATA "10,4">
|
||||
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
|
||||
<!ELEMENT twExecVer (#PCDATA)>
|
||||
<!ELEMENT twCopyright (#PCDATA)>
|
||||
<!ELEMENT twCmdLine (#PCDATA)>
|
||||
<!ELEMENT twDesign (#PCDATA)>
|
||||
<!ELEMENT twPCF (#PCDATA)>
|
||||
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
|
||||
<!ELEMENT twDevName (#PCDATA)>
|
||||
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
|
||||
<!ELEMENT twSpeedGrade (#PCDATA)>
|
||||
<!ELEMENT twSpeedVer (#PCDATA)>
|
||||
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
|
||||
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
|
||||
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
|
||||
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
|
||||
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
|
||||
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twItemLimit (#PCDATA)>
|
||||
<!ELEMENT twUnconst EMPTY>
|
||||
<!ELEMENT twUnconstLimit (#PCDATA)>
|
||||
<!ELEMENT twEnvVar EMPTY>
|
||||
<!ATTLIST twEnvVar name CDATA #REQUIRED>
|
||||
<!ATTLIST twEnvVar description CDATA #REQUIRED>
|
||||
<!ELEMENT twWarn (#PCDATA)>
|
||||
<!ELEMENT twInfo (#PCDATA)>
|
||||
<!ELEMENT twDebug (#PCDATA)>
|
||||
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
|
||||
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
|
||||
<!ELEMENT twProc (#PCDATA)>
|
||||
<!ELEMENT twTemp (#PCDATA)>
|
||||
<!ELEMENT twVolt (#PCDATA)>
|
||||
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
|
||||
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
|
||||
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
|
||||
<!ELEMENT twCycles (twSigConn+)>
|
||||
<!ATTLIST twCycles twNum CDATA #REQUIRED>
|
||||
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
|
||||
<!ELEMENT twSig (#PCDATA)>
|
||||
<!ELEMENT twDriver (#PCDATA)>
|
||||
<!ELEMENT twLoad (#PCDATA)>
|
||||
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
|
||||
<!ATTLIST twConst twConstType (NET |
|
||||
NETDELAY |
|
||||
NETSKEW |
|
||||
PATH |
|
||||
DEFPERIOD |
|
||||
UNCONSTPATH |
|
||||
DEFPATH |
|
||||
PATH2SETUP |
|
||||
UNCONSTPATH2SETUP |
|
||||
PATHCLASS |
|
||||
PATHDELAY |
|
||||
PERIOD |
|
||||
FREQUENCY |
|
||||
PATHBLOCK |
|
||||
OFFSET |
|
||||
OFFSETIN |
|
||||
OFFSETINCLOCK |
|
||||
UNCONSTOFFSETINCLOCK |
|
||||
OFFSETINDELAY |
|
||||
OFFSETINMOD |
|
||||
OFFSETOUT |
|
||||
OFFSETOUTCLOCK |
|
||||
UNCONSTOFFSETOUTCLOCK |
|
||||
OFFSETOUTDELAY |
|
||||
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
|
||||
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
|
||||
twEndPtCnt?,
|
||||
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
|
||||
<!ELEMENT twConstName (#PCDATA)>
|
||||
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
|
||||
<!ATTLIST twConstHead uID CDATA #IMPLIED>
|
||||
<!ELEMENT twItemCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCnt (#PCDATA)>
|
||||
<!ELEMENT twErrCntEndPt (#PCDATA)>
|
||||
<!ELEMENT twErrCntSetup (#PCDATA)>
|
||||
<!ELEMENT twErrCntHold (#PCDATA)>
|
||||
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twEndPtCnt (#PCDATA)>
|
||||
<!ELEMENT twPathErrCnt (#PCDATA)>
|
||||
<!ELEMENT twMinPer (#PCDATA) >
|
||||
<!ELEMENT twFootnote EMPTY>
|
||||
<!ATTLIST twFootnote number CDATA #REQUIRED>
|
||||
<!ELEMENT twMaxDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFreq (#PCDATA)>
|
||||
<!ELEMENT twMinOff (#PCDATA)>
|
||||
<!ELEMENT twMaxOff (#PCDATA)>
|
||||
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
|
||||
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
|
||||
<!ELEMENT twTIGName (#PCDATA)>
|
||||
<!ELEMENT twInstantiated (#PCDATA)>
|
||||
<!ELEMENT twBlocked (#PCDATA)>
|
||||
<!ELEMENT twRacePathRpt (twRacePath+)>
|
||||
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
|
||||
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
|
||||
twSimpleMinPath CDATA #IMPLIED>
|
||||
<!ELEMENT twTotDel (#PCDATA)>
|
||||
<!ELEMENT twSrc (#PCDATA)>
|
||||
<!ATTLIST twSrc BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDest (#PCDATA)>
|
||||
<!ATTLIST twDest BELType CDATA #IMPLIED>
|
||||
<!ELEMENT twDel (#PCDATA)>
|
||||
<!ELEMENT twSUTime (#PCDATA)>
|
||||
<!ELEMENT twTotPathDel (#PCDATA)>
|
||||
<!ELEMENT twClkSkew (#PCDATA)>
|
||||
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
|
||||
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
|
||||
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
|
||||
<!ELEMENT twSlack (#PCDATA)>
|
||||
<!ELEMENT twDelConst (#PCDATA)>
|
||||
<!ELEMENT tw2Phase EMPTY>
|
||||
<!ELEMENT twClkUncert (#PCDATA)>
|
||||
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
|
||||
fDCMJit CDATA #IMPLIED
|
||||
fPhaseErr CDATA #IMPLIED
|
||||
sEqu CDATA #IMPLIED>
|
||||
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
|
||||
<!ELEMENT twPathRptBanner (#PCDATA)>
|
||||
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
|
||||
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twOff (#PCDATA)>
|
||||
<!ELEMENT twGuaranteed EMPTY>
|
||||
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
|
||||
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
|
||||
<!ELEMENT twClkDel (#PCDATA)>
|
||||
<!ELEMENT twClkSrc (#PCDATA)>
|
||||
<!ELEMENT twClkDest (#PCDATA)>
|
||||
<!ELEMENT twGuarInSetup (#PCDATA)>
|
||||
<!ELEMENT twOffSrc (#PCDATA)>
|
||||
<!ELEMENT twOffDest (#PCDATA)>
|
||||
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
|
||||
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
|
||||
<!ELEMENT twDataDel (#PCDATA)>
|
||||
<!ELEMENT twDataSrc (#PCDATA)>
|
||||
<!ELEMENT twDataDest (#PCDATA)>
|
||||
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
|
||||
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
|
||||
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
|
||||
<!ELEMENT twLogLvls (#PCDATA)>
|
||||
<!ELEMENT twSrcSite (#PCDATA)>
|
||||
<!ELEMENT twSrcClk (#PCDATA)>
|
||||
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
|
||||
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
|
||||
<!ELEMENT twDelInfo (#PCDATA)>
|
||||
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twSite (#PCDATA)>
|
||||
<!ELEMENT twDelType (#PCDATA)>
|
||||
<!ELEMENT twFanCnt (#PCDATA)>
|
||||
<!ELEMENT twComp (#PCDATA)>
|
||||
<!ELEMENT twNet (#PCDATA)>
|
||||
<!ELEMENT twBEL (#PCDATA)>
|
||||
<!ELEMENT twLogDel (#PCDATA)>
|
||||
<!ELEMENT twRouteDel (#PCDATA)>
|
||||
<!ELEMENT twDestClk (#PCDATA)>
|
||||
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
|
||||
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
|
||||
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
|
||||
<!ELEMENT twPctLog (#PCDATA)>
|
||||
<!ELEMENT twPctRoute (#PCDATA)>
|
||||
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
|
||||
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
|
||||
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
|
||||
<!ELEMENT twTimeConst (#PCDATA)>
|
||||
<!ELEMENT twAbsSlack (#PCDATA)>
|
||||
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
|
||||
<!ELEMENT twSkew (#PCDATA)>
|
||||
<!ELEMENT twDetNet (twNetDel*)>
|
||||
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
|
||||
<!ELEMENT twNetDelInfo (#PCDATA)>
|
||||
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
|
||||
<!ELEMENT twDetSkewNet (twNetSkew*)>
|
||||
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
|
||||
<!ELEMENT twClkSkewLimit EMPTY>
|
||||
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
|
||||
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollupTable (twConstRollup*)>
|
||||
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
|
||||
<!ELEMENT twConstRollup EMPTY>
|
||||
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
|
||||
<!ELEMENT twConstList (twConstListItem)*>
|
||||
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
|
||||
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
|
||||
<!ELEMENT twNotMet EMPTY>
|
||||
<!ELEMENT twReqVal (#PCDATA)>
|
||||
<!ELEMENT twActVal (#PCDATA)>
|
||||
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
|
||||
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
|
||||
<!ELEMENT twConstStats (twConstName)>
|
||||
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
|
||||
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
|
||||
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
|
||||
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
|
||||
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
|
||||
<!ELEMENT twConstData EMPTY>
|
||||
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
|
||||
best CDATA #IMPLIED requested CDATA #IMPLIED
|
||||
errors CDATA #IMPLIED
|
||||
score CDATA #IMPLIED>
|
||||
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
|
||||
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
|
||||
<!ELEMENT twTimeGrpName (#PCDATA)>
|
||||
<!ELEMENT twCompList (twCompName+)>
|
||||
<!ELEMENT twCompName (#PCDATA)>
|
||||
<!ELEMENT twSigList (twSigName+)>
|
||||
<!ELEMENT twSigName (#PCDATA)>
|
||||
<!ELEMENT twBELList (twBELName+)>
|
||||
<!ELEMENT twBELName (#PCDATA)>
|
||||
<!ELEMENT twBlockList (twBlockName+)>
|
||||
<!ELEMENT twBlockName (#PCDATA)>
|
||||
<!ELEMENT twMacList (twMacName+)>
|
||||
<!ELEMENT twMacName (#PCDATA)>
|
||||
<!ELEMENT twPinList (twPinName+)>
|
||||
<!ELEMENT twPinName (#PCDATA)>
|
||||
<!ELEMENT twUnmetConstCnt (#PCDATA)>
|
||||
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
|
||||
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
|
||||
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
|
||||
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
|
||||
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
|
||||
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
|
||||
<!ELEMENT twSU2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twH2ClkTime (#PCDATA)>
|
||||
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
|
||||
<!ELEMENT twClk2Pad (twDest, twTime)>
|
||||
<!ELEMENT twTime (#PCDATA)>
|
||||
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
|
||||
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
|
||||
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2Out EMPTY>
|
||||
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
|
||||
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
|
||||
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
|
||||
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
|
||||
<!ELEMENT twRiseRise (#PCDATA)>
|
||||
<!ELEMENT twFallRise (#PCDATA)>
|
||||
<!ELEMENT twRiseFall (#PCDATA)>
|
||||
<!ELEMENT twFallFall (#PCDATA)>
|
||||
<!ELEMENT twPad2PadList (twPad2Pad+)>
|
||||
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
|
||||
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
|
||||
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
|
||||
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
|
||||
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
|
||||
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
|
||||
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
|
||||
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
|
||||
<!ELEMENT twOffOutTblRow EMPTY>
|
||||
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
|
||||
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
|
||||
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
|
||||
<!ELEMENT twNonDedClk (#PCDATA)>
|
||||
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
|
||||
<!ELEMENT twScore (#PCDATA)>
|
||||
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
|
||||
<!ELEMENT twPathCnt (#PCDATA)>
|
||||
<!ELEMENT twNetCnt (#PCDATA)>
|
||||
<!ELEMENT twConnCnt (#PCDATA)>
|
||||
<!ELEMENT twPct (#PCDATA)>
|
||||
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
|
||||
<!ELEMENT twMaxCombDel (#PCDATA)>
|
||||
<!ELEMENT twMaxFromToDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetDel (#PCDATA)>
|
||||
<!ELEMENT twMaxNetSkew (#PCDATA)>
|
||||
<!ELEMENT twMaxInAfterClk (#PCDATA)>
|
||||
<!ELEMENT twMinInBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
|
||||
<!ELEMENT twMinOutAfterClk (#PCDATA)>
|
||||
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
|
||||
<!ELEMENT twTimestamp (#PCDATA)>
|
||||
<!ELEMENT twFootnoteExplanation EMPTY>
|
||||
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
|
||||
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
|
||||
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
|
||||
<!ELEMENT twClientName (#PCDATA)>
|
||||
<!ELEMENT twAttrList (twAttrListItem)*>
|
||||
<!ELEMENT twAttrListItem (twName, twValue*)>
|
||||
<!ELEMENT twName (#PCDATA)>
|
||||
<!ELEMENT twValue (#PCDATA)>
|
||||
]>
|
||||
<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n
|
||||
3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
|
||||
|
||||
</twCmdLine><twDesign>main.ncd</twDesign><twDesignPath>main.ncd</twDesignPath><twPCF>main.pcf</twPCF><twPcfPath>main.pcf</twPcfPath><twDevInfo arch="spartan3e" pkg="cp132"><twDevName>xc3s250e</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2012-04-23</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="6">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="7">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="8" twNameLen="15"><twClk2OutList anchorID="9" twDestWidth="6" twPhaseWidth="9"><twSrc>CLK</twSrc><twClk2Out twOutPad = "HS" twMinTime = "5.125" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.320" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<0>" twMinTime = "5.717" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.061" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<1>" twMinTime = "5.710" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.052" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<2>" twMinTime = "5.948" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.348" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<3>" twMinTime = "6.121" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.565" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<4>" twMinTime = "6.100" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.538" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<5>" twMinTime = "6.953" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.606" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<6>" twMinTime = "6.780" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.389" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB<7>" twMinTime = "6.453" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.981" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "VS" twMinTime = "5.372" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.627" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="10" twDestWidth="3"><twDest>CLK</twDest><twClk2SU><twSrc>CLK</twSrc><twRiseRise>5.493</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Thu Feb 21 20:21:26 2013 </twTimestamp></twFoot><twClientInfo anchorID="11"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
|
||||
|
||||
Peak Memory Usage: 129 MB
|
||||
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>
|
||||
9
main.unroutes
Normal file
9
main.unroutes
Normal file
|
|
@ -0,0 +1,9 @@
|
|||
Release 14.1 - par P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Thu Feb 21 20:21:23 2013
|
||||
|
||||
All signals are completely routed.
|
||||
|
||||
|
||||
|
||||
22
main.ut
Normal file
22
main.ut
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
-w
|
||||
-g DebugBitstream:No
|
||||
-g Binary:no
|
||||
-g CRC:Enable
|
||||
-g ConfigRate:1
|
||||
-g ProgPin:PullUp
|
||||
-g DonePin:PullUp
|
||||
-g TckPin:PullUp
|
||||
-g TdiPin:PullUp
|
||||
-g TdoPin:PullUp
|
||||
-g TmsPin:PullUp
|
||||
-g UnusedPin:PullDown
|
||||
-g UserID:0xFFFFFFFF
|
||||
-g DCMShutdown:Disable
|
||||
-g StartUpClk:CClk
|
||||
-g DONE_cycle:4
|
||||
-g GTS_cycle:5
|
||||
-g GWE_cycle:6
|
||||
-g LCK_cycle:NoWait
|
||||
-g Security:None
|
||||
-g DonePipe:Yes
|
||||
-g DriveDone:No
|
||||
68
main.vhd
Normal file
68
main.vhd
Normal file
|
|
@ -0,0 +1,68 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity main is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
RGB : out std_logic_vector(7 downto 0);
|
||||
|
||||
HS : out std_logic;
|
||||
VS : out std_logic
|
||||
);
|
||||
end main;
|
||||
|
||||
architecture Behavioral of main is
|
||||
component vga is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
IRGB : in std_logic_vector(7 downto 0);
|
||||
|
||||
RGB : out std_logic_vector(7 downto 0);
|
||||
|
||||
W : out std_logic;
|
||||
X : out std_logic_vector(9 downto 0);
|
||||
Y : out std_logic_vector(9 downto 0);
|
||||
|
||||
VS : out std_logic;
|
||||
HS : out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal inrgb : std_logic_vector(7 downto 0) := "00000000";
|
||||
|
||||
signal w : std_logic;
|
||||
signal x : std_logic_vector(9 downto 0);
|
||||
signal y : std_logic_vector(9 downto 0);
|
||||
begin
|
||||
|
||||
VGADriver : component vga port map (
|
||||
CLK => CLK,
|
||||
LED => LED,
|
||||
HS => HS,
|
||||
VS => VS,
|
||||
RGB => RGB,
|
||||
IRGB => inrgb,
|
||||
W => w,
|
||||
X => x,
|
||||
Y => y
|
||||
);
|
||||
|
||||
process (CLK) begin
|
||||
if w = '1' then
|
||||
if x >= 300 and x <= 340 and y >= 220 and y <= 260 then
|
||||
inrgb <= "11100011";
|
||||
else
|
||||
inrgb <= "00011100";
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
3
main.xpi
Normal file
3
main.xpi
Normal file
|
|
@ -0,0 +1,3 @@
|
|||
PROGRAM=PAR
|
||||
STATE=ROUTED
|
||||
TIMESPECS_MET=OFF
|
||||
56
main.xst
Normal file
56
main.xst
Normal file
|
|
@ -0,0 +1,56 @@
|
|||
set -tmpdir "xst/projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn main.prj
|
||||
-ifmt mixed
|
||||
-ofn main
|
||||
-ofmt NGC
|
||||
-p xc3s250e-5-cp132
|
||||
-top main
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
-rtlview Yes
|
||||
-glob_opt AllClockNets
|
||||
-read_cores YES
|
||||
-write_timing_constraints NO
|
||||
-cross_clock_analysis NO
|
||||
-hierarchy_separator /
|
||||
-bus_delimiter <>
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract Yes
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract Yes
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-mult_style Auto
|
||||
-iobuf YES
|
||||
-max_fanout 100000
|
||||
-bufg 24
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Yes
|
||||
-use_sync_set Yes
|
||||
-use_sync_reset Yes
|
||||
-iob Auto
|
||||
-equivalent_register_removal YES
|
||||
-slice_utilization_ratio_maxmargin 5
|
||||
8
main_bitgen.xwbt
Normal file
8
main_bitgen.xwbt
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
INTSTYLE=ise
|
||||
INFILE=C:\fpga\pong\main.ncd
|
||||
OUTFILE=C:\fpga\pong\main.bit
|
||||
FAMILY=Spartan3E
|
||||
PART=xc3s250e-5cp132
|
||||
WORKINGDIR=C:\fpga\pong
|
||||
LICENSE=WebPack
|
||||
USER_INFO=__0_0_0
|
||||
509
main_envsettings.html
Normal file
509
main_envsettings.html
Normal file
|
|
@ -0,0 +1,509 @@
|
|||
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<center><big><big><b>System Settings</b></big></big></center><br>
|
||||
<A NAME="Environment Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Environment Variable</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATHEXT</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
<td>.COM;<br>.EXE;<br>.BAT;<br>.CMD;<br>.VBS;<br>.VBE;<br>.JS;<br>.JSE;<br>.WSF;<br>.WSH;<br>.MSC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Path</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\Vivado\2012.1\bin;<br>C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\common\lib\nt;<br>C:\GTK\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\windows\system32;<br>C:\windows;<br>C:\windows\System32\Wbem;<br>C:\windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jre6\bin;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files (x86)\VisualSVN\bin;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>L:\fortran\g95\bin</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\Vivado\2012.1\bin;<br>C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\common\lib\nt;<br>C:\GTK\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\windows\system32;<br>C:\windows;<br>C:\windows\System32\Wbem;<br>C:\windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jre6\bin;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files (x86)\VisualSVN\bin;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>L:\fortran\g95\bin</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\Vivado\2012.1\bin;<br>C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\common\lib\nt;<br>C:\GTK\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\windows\system32;<br>C:\windows;<br>C:\windows\System32\Wbem;<br>C:\windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jre6\bin;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files (x86)\VisualSVN\bin;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>L:\fortran\g95\bin</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;<br>C:\Xilinx\Vivado\2012.1\bin;<br>C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;<br>C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;<br>C:\Xilinx\14.1\ISE_DS\common\bin\nt;<br>C:\Xilinx\14.1\ISE_DS\common\lib\nt;<br>C:\GTK\bin;<br>C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;<br>C:\windows\system32;<br>C:\windows;<br>C:\windows\System32\Wbem;<br>C:\windows\System32\WindowsPowerShell\v1.0\;<br>C:\Program Files (x86)\Java\jre6\bin;<br>c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;<br>c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;<br>C:\Program Files\TortoiseSVN\bin;<br>C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;<br>C:\Program Files (x86)\VisualSVN\bin;<br>C:\Program Files (x86)\QuickTime\QTSystem\;<br>C:\Program Files\MATLAB\R2011a\runtime\win64;<br>C:\Program Files\MATLAB\R2011a\bin;<br>C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;<br>C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;<br>C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;<br>C:\Program Files\Microsoft\Web Platform Installer\;<br>C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;<br>C:\Program Files\IVI Foundation\VISA\Win64\Bin\;<br>C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;<br>L:\fortran\g95\bin</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE\</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\ISE</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\EDK</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\EDK</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\PlanAhead</td>
|
||||
<td>C:\Xilinx\14.1\ISE_DS\PlanAhead</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_VIVADO</td>
|
||||
<td>C:\Xilinx\Vivado\2012.1</td>
|
||||
<td>C:\Xilinx\Vivado\2012.1</td>
|
||||
<td>C:\Xilinx\Vivado\2012.1</td>
|
||||
<td>C:\Xilinx\Vivado\2012.1</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifn</td>
|
||||
<td> </td>
|
||||
<td>main.prj</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifmt</td>
|
||||
<td> </td>
|
||||
<td>mixed</td>
|
||||
<td>MIXED</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>main</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofmt</td>
|
||||
<td> </td>
|
||||
<td>NGC</td>
|
||||
<td>NGC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc3s250e-5-cp132</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-top</td>
|
||||
<td> </td>
|
||||
<td>main</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>SPEED</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>as_optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>ALLCLOCKNETS</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-read_cores</td>
|
||||
<td>Read Cores</td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-write_timing_constraints</td>
|
||||
<td>Write Timing Constraints</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cross_clock_analysis</td>
|
||||
<td>Cross Clock Analysis</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
<td>Bus Delimiter</td>
|
||||
<td><></td>
|
||||
<td><></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio</td>
|
||||
<td>Slice Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bram_utilization_ratio</td>
|
||||
<td>BRAM Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100%</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-verilog2001</td>
|
||||
<td>Verilog 2001</td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_style</td>
|
||||
<td> </td>
|
||||
<td>LUT</td>
|
||||
<td>LUT</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-shreg_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-auto_bram_packing</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-async_to_sync</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mult_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-max_fanout</td>
|
||||
<td> </td>
|
||||
<td>100000</td>
|
||||
<td>500</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bufg</td>
|
||||
<td> </td>
|
||||
<td>24</td>
|
||||
<td>24</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_balancing</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-optimize_primitives</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_clock_enable</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_set</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_reset</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iob</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio_maxmargin</td>
|
||||
<td> </td>
|
||||
<td>5</td>
|
||||
<td>0%</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Translation Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dd</td>
|
||||
<td> </td>
|
||||
<td>_ngo</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc3s250e-cp132-5</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-uc</td>
|
||||
<td> </td>
|
||||
<td>pins.ucf</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Map Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ir</td>
|
||||
<td>Use RLOC Constraints</td>
|
||||
<td>OFF</td>
|
||||
<td>OFF</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cm</td>
|
||||
<td>Optimization Strategy (Cover Mode)</td>
|
||||
<td>area</td>
|
||||
<td>area</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-o</td>
|
||||
<td> </td>
|
||||
<td>main_map.ncd</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-pr</td>
|
||||
<td>Pack I/O Registers/Latches into IOBs</td>
|
||||
<td>off</td>
|
||||
<td>off</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc3s250e-cp132-5</td>
|
||||
<td>None</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Place and Route Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-t</td>
|
||||
<td> </td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-intstyle</td>
|
||||
<td> </td>
|
||||
<td>ise</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ol</td>
|
||||
<td>Place & Route Effort Level (Overall)</td>
|
||||
<td>high</td>
|
||||
<td>std</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-w</td>
|
||||
<td> </td>
|
||||
<td>true</td>
|
||||
<td>false</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Operating System Information</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHz</td>
|
||||
<td>Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHz</td>
|
||||
<td>Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHz</td>
|
||||
<td>Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHz</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>ALECO-PC</td>
|
||||
<td>ALECO-PC</td>
|
||||
<td>ALECO-PC</td>
|
||||
<td>ALECO-PC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
<td>Microsoft Windows 7 , 64-bit</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>major release (build 7600)</td>
|
||||
<td>major release (build 7600)</td>
|
||||
<td>major release (build 7600)</td>
|
||||
<td>major release (build 7600)</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
3
main_guide.ncd
Normal file
3
main_guide.ncd
Normal file
File diff suppressed because one or more lines are too long
71
main_map.map
Normal file
71
main_map.map
Normal file
|
|
@ -0,0 +1,71 @@
|
|||
Release 14.1 Map P.15xf (nt)
|
||||
Xilinx Map Application Log File for Design 'main'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off
|
||||
-c 100 -o main_map.ncd main.ngd main.pcf
|
||||
Target Device : xc3s250e
|
||||
Target Package : cp132
|
||||
Target Speed : -5
|
||||
Mapper Version : spartan3e -- $Revision: 1.55 $
|
||||
Mapped Date : Thu Feb 21 20:21:08 2013
|
||||
|
||||
Mapping design into LUTs...
|
||||
Running directed packing...
|
||||
Running delay-based LUT packing...
|
||||
Running related packing...
|
||||
Updating timing models...
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
|
||||
Design Summary:
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Logic Utilization:
|
||||
Total Number Slice Registers: 47 out of 4,896 1%
|
||||
Number used as Flip Flops: 45
|
||||
Number used as Latches: 2
|
||||
Number of 4 input LUTs: 58 out of 4,896 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 52 out of 2,448 2%
|
||||
Number of Slices containing only related logic: 52 out of 52 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 52 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 92 out of 4,896 1%
|
||||
Number used as logic: 58
|
||||
Number used as a route-thru: 34
|
||||
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
Number of bonded IOBs: 19 out of 92 20%
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.67
|
||||
|
||||
Peak Memory Usage: 209 MB
|
||||
Total REAL time to MAP completion: 1 secs
|
||||
Total CPU time to MAP completion: 1 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Mapping completed.
|
||||
See MAP report file "main_map.mrp" for details.
|
||||
169
main_map.mrp
Normal file
169
main_map.mrp
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
Release 14.1 Map P.15xf (nt)
|
||||
Xilinx Mapping Report File for Design 'main'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off
|
||||
-c 100 -o main_map.ncd main.ngd main.pcf
|
||||
Target Device : xc3s250e
|
||||
Target Package : cp132
|
||||
Target Speed : -5
|
||||
Mapper Version : spartan3e -- $Revision: 1.55 $
|
||||
Mapped Date : Thu Feb 21 20:21:08 2013
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Logic Utilization:
|
||||
Total Number Slice Registers: 47 out of 4,896 1%
|
||||
Number used as Flip Flops: 45
|
||||
Number used as Latches: 2
|
||||
Number of 4 input LUTs: 58 out of 4,896 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 52 out of 2,448 2%
|
||||
Number of Slices containing only related logic: 52 out of 52 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 52 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 92 out of 4,896 1%
|
||||
Number used as logic: 58
|
||||
Number used as a route-thru: 34
|
||||
|
||||
The Slice Logic Distribution report is not meaningful if the design is
|
||||
over-mapped for a non-slice resource or if Placement fails.
|
||||
|
||||
Number of bonded IOBs: 19 out of 92 20%
|
||||
Number of BUFGMUXs: 1 out of 24 4%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 2.67
|
||||
|
||||
Peak Memory Usage: 209 MB
|
||||
Total REAL time to MAP completion: 1 secs
|
||||
Total CPU time to MAP completion: 1 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Timing Report
|
||||
Section 11 - Configuration String Information
|
||||
Section 12 - Control Set Information
|
||||
Section 13 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
2 block(s) optimized away
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
Optimized Block(s):
|
||||
TYPE BLOCK
|
||||
GND XST_GND
|
||||
VCC XST_VCC
|
||||
|
||||
To enable printing of redundant blocks removed and signals merged, set the
|
||||
detailed map report option and rerun map.
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Term | Strength | Rate | | | Delay |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| CLK | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 |
|
||||
| HS | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| LED<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| LED<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
|
||||
| RGB<0> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<1> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<2> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<3> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<4> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<5> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<6> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| RGB<7> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
| VS | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Timing Report
|
||||
--------------------------
|
||||
This design was not run using timing mode.
|
||||
|
||||
Section 11 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 12 - Control Set Information
|
||||
------------------------------------
|
||||
No control set information for this architecture.
|
||||
|
||||
Section 13 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
||||
3
main_map.ncd
Normal file
3
main_map.ncd
Normal file
File diff suppressed because one or more lines are too long
3
main_map.ngm
Normal file
3
main_map.ngm
Normal file
File diff suppressed because one or more lines are too long
303
main_map.xrpt
Normal file
303
main_map.xrpt
Normal file
|
|
@ -0,0 +1,303 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.1">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Map" timeStamp="Thu Feb 21 20:21:10 2013">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.1\bin;C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.1\ISE_DS\common\bin\nt;C:\Xilinx\14.1\ISE_DS\common\lib\nt;C:\GTK\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\windows\system32;C:\windows;C:\windows\System32\Wbem;C:\windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Java\jre6\bin;c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\VisualSVN\bin;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files\Microsoft\Web Platform Installer\;C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;L:\fortran\g95\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item stringID="variable" value="XILINX_VIVADO"/>
|
||||
<item stringID="value" value="C:\Xilinx\Vivado\2012.1"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ALECO-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz"/>
|
||||
<item stringID="speed" value="3191 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_OPTION_SUMMARY">
|
||||
<item DEFAULT="OFF" label="-ir" stringID="MAP_IGNORERLOCS" value="OFF"/>
|
||||
<item DEFAULT="area" label="-cm" stringID="MAP_COVER_MODE" value="area"/>
|
||||
<item DEFAULT="None" label="-intstyle" stringID="MAP_INTSTYLE" value="ise"/>
|
||||
<item DEFAULT="None" label="-o" stringID="MAP_OUTFILE" value="main_map.ncd"/>
|
||||
<item DEFAULT="off" label="-pr" stringID="MAP_PACK_INTERNAL" value="off"/>
|
||||
<item DEFAULT="None" label="-p" stringID="MAP_PARTNAME" value="xc3s250e-cp132-5"/>
|
||||
</section>
|
||||
<task stringID="MAP_PACK_REPORT">
|
||||
<section stringID="MAP_DESIGN_INFORMATION">
|
||||
<item stringID="MAP_PART" value="3s250ecp132-5"/>
|
||||
<item stringID="MAP_DEVICE" value="xc3s250e"/>
|
||||
<item stringID="MAP_ARCHITECTURE" value="spartan3e"/>
|
||||
<item stringID="MAP_PACKAGE" value="cp132"/>
|
||||
<item stringID="MAP_SPEED" value="-5"/>
|
||||
</section>
|
||||
<section stringID="MAP_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
|
||||
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="214240"/>
|
||||
<item stringID="MAP_TOTAL_REAL_TIME" value="1 secs "/>
|
||||
<item stringID="MAP_TOTAL_CPU_TIME" value="1 secs "/>
|
||||
</section>
|
||||
<section stringID="MAP_SLICE_REPORTING">
|
||||
<item AVAILABLE="4896" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="47">
|
||||
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="45"/>
|
||||
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="2"/>
|
||||
</item>
|
||||
<item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="92">
|
||||
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="34"/>
|
||||
</item>
|
||||
<item AVAILABLE="2448" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="52">
|
||||
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_REPORTING">
|
||||
<section stringID="MAP_IOB_DATA">
|
||||
<item AVAILABLE="92" dataType="int" stringID="MAP_AGG_BONDED_IO" value="19"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_HARD_IP_REPORTING">
|
||||
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="1"/>
|
||||
</section>
|
||||
<section stringID="MAP_MACRO_RPM_REPORTING">
|
||||
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
|
||||
<item dataType="int" stringID="MAP_RPMS" value="0"/>
|
||||
</section>
|
||||
<section stringID="MAP_IOB_PROPERTIES">
|
||||
<table stringID="MAP_IOB_TABLE">
|
||||
<column label="IOB
Name" sort="smart" stringID="IOB_NAME"/>
|
||||
<column stringID="Type"/>
|
||||
<column stringID="Direction"/>
|
||||
<column label="IO
Standard" sort="smart" stringID="IO_STANDARD"/>
|
||||
<column label="Diff
Term" stringID="DIFF_TERM"/>
|
||||
<column label="Drive
Strength" stringID="DRIVE_STRENGTH"/>
|
||||
<column label="Slew
Rate" stringID="SLEW_RATE"/>
|
||||
<column label="Reg
(s)" stringID="REGS"/>
|
||||
<column stringID="Resistor"/>
|
||||
<column label="IOB
Delay" stringID="IOB_DELAY"/>
|
||||
<row stringID="row" value="1">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="CLK"/>
|
||||
<item stringID="Type" value="IBUF"/>
|
||||
<item stringID="Direction" value="INPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="HS"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="7">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="8">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="9">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="10">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="LED<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="12"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="SLOW"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="11">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<0>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="12">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<1>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="13">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<2>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="14">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<3>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="15">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<4>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="16">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<5>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="17">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<6>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="18">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="RGB<7>"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
<row stringID="row" value="19">
|
||||
<item label="IOB
Name" sort="smart" stringID="IOB_NAME" value="VS"/>
|
||||
<item stringID="Type" value="IOB"/>
|
||||
<item stringID="Direction" value="OUTPUT"/>
|
||||
<item label="IO
Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS33"/>
|
||||
<item label="Drive
Strength" stringID="DRIVE_STRENGTH" value="8"/>
|
||||
<item label="Slew
Rate" stringID="SLEW_RATE" value="FAST"/>
|
||||
<item label="IOB
Delay" stringID="IOB_DELAY" value="0 / 0"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="MAP_RPM_MACROS">
|
||||
<section stringID="MAP_SHAPE_SECTION">
|
||||
<item dataType="int" stringID="MAP_NUM_SHAPE" value="5"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="MAP_GUIDE_REPORT"/>
|
||||
<section stringID="MAP_AREA_GROUPS_PARTITIONS"/>
|
||||
<section stringID="MAP_TIMING_REPORT"/>
|
||||
<section stringID="MAP_CONFIGURATION_STRING_DETAILS"/>
|
||||
<section stringID="MAP_GENERAL_CONFIG_DATA">
|
||||
<item stringID="MAP_DISABLE_ATTR" value="LOW"/>
|
||||
</section>
|
||||
<section stringID="MAP_CONTROL_SET_INFORMATION"/>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
127
main_ngdbuild.xrpt
Normal file
127
main_ngdbuild.xrpt
Normal file
|
|
@ -0,0 +1,127 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.1">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="NgdBuild" timeStamp="Thu Feb 21 20:21:06 2013">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.1\bin;C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.1\ISE_DS\common\bin\nt;C:\Xilinx\14.1\ISE_DS\common\lib\nt;C:\GTK\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\windows\system32;C:\windows;C:\windows\System32\Wbem;C:\windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Java\jre6\bin;c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\VisualSVN\bin;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files\Microsoft\Web Platform Installer\;C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;L:\fortran\g95\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item stringID="variable" value="XILINX_VIVADO"/>
|
||||
<item stringID="value" value="C:\Xilinx\Vivado\2012.1"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ALECO-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz"/>
|
||||
<item stringID="speed" value="3191 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<task stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<section stringID="NGDBUILD_OPTION_SUMMARY">
|
||||
<item DEFAULT="None" label="-intstyle" stringID="NGDBUILD_intstyle" value="ise"/>
|
||||
<item DEFAULT="None" label="-dd" stringID="NGDBUILD_output_dir" value="_ngo"/>
|
||||
<item DEFAULT="None" label="-p" stringID="NGDBUILD_partname" value="xc3s250e-cp132-5"/>
|
||||
<item DEFAULT="None" label="-uc" stringID="NGDBUILD_ucf_file" value="pins.ucf"/>
|
||||
</section>
|
||||
</task>
|
||||
<task stringID="NGDBUILD_REPORT">
|
||||
<section stringID="NGDBUILD_DESIGN_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_ERRORS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_WARNINGS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_FILTERED_INFOS" value="0"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="45"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="18"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="50"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="20"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="13"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="10"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LD" value="2"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="33"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="6"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="29"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="4"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="45"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="18"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
|
||||
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="50"/>
|
||||
</section>
|
||||
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
|
||||
<section stringID="NGDBUILD_CORE_INSTANCES"/>
|
||||
</section>
|
||||
</task>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
163
main_pad.csv
Normal file
163
main_pad.csv
Normal file
|
|
@ -0,0 +1,163 @@
|
|||
#Release 14.1 - par P.15xf (nt)
|
||||
#Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
#Thu Feb 21 20:21:23 2013
|
||||
|
||||
#
|
||||
## NOTE: This file is designed to be imported into a spreadsheet program
|
||||
# such as Microsoft Excel for viewing, printing and sorting. The |
|
||||
# character is used as the data field separator. This file is also designed
|
||||
# to support parsing.
|
||||
#
|
||||
#INPUT FILE: main_map.ncd
|
||||
#OUTPUT FILE: main_pad.csv
|
||||
#PART TYPE: xc3s250e
|
||||
#SPEED GRADE: -5
|
||||
#PACKAGE: cp132
|
||||
#
|
||||
# Pinout by Pin Number:
|
||||
#
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
|
||||
A1,,,PROG_B,,,,,,,,,,,,
|
||||
A2,,,TDI,,,,,,,,,,,,
|
||||
A3,,DIFFM,IO_L11P_0,UNUSED,,0,,,,,,,,,
|
||||
A4,,,GND,,,,,,,,,,,,
|
||||
A5,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
A6,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
A7,,DIFFM,IO_L07P_0/GCLK10,UNUSED,,0,,,,,,,,,
|
||||
A8,,,GND,,,,,,,,,,,,
|
||||
A9,,DIFFS,IO_L05N_0/GCLK7,UNUSED,,0,,,,,,,,,
|
||||
A10,,DIFFM,IO_L04P_0/GCLK4,UNUSED,,0,,,,,,,,,
|
||||
A11,,,VCCINT,,,,,,,,1.2,,,,
|
||||
A12,,DIFFS,IO_L02N_0,UNUSED,,0,,,,,,,,,
|
||||
A13,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,,
|
||||
A14,,,TDO,,,,,,,,,,,,
|
||||
B1,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,,
|
||||
B2,,DIFFM,IO_L01P_3,UNUSED,,3,,,,,,,,,
|
||||
B3,,DIFFS,IO_L11N_0/HSWAP,UNUSED,,0,,,,,,,,,
|
||||
B4,,DIFFM,IO_L10P_0,UNUSED,,0,,,,,,,,,
|
||||
B5,,DIFFM,IO_L09P_0,UNUSED,,0,,,,,,,,,
|
||||
B6,,DIFFM,IO_L08P_0,UNUSED,,0,,,,,,,,,
|
||||
B7,,DIFFS,IO_L07N_0/GCLK11,UNUSED,,0,,,,,,,,,
|
||||
B8,,DIFFMI,IP_L06P_0/GCLK8,UNUSED,,0,,,,,,,,,
|
||||
B9,,DIFFM,IO_L05P_0/GCLK6,UNUSED,,0,,,,,,,,,
|
||||
B10,,,VCCO_0,,,0,,,,,any******,,,,
|
||||
B11,,DIFFS,IO_L03N_0/VREF_0,UNUSED,,0,,,,,,,,,
|
||||
B12,,DIFFM,IO_L02P_0,UNUSED,,0,,,,,,,,,
|
||||
B13,,,TCK,,,,,,,,,,,,
|
||||
B14,,,TMS,,,,,,,,,,,,
|
||||
C1,,,GND,,,,,,,,,,,,
|
||||
C2,,DIFFS,IO_L02N_3,UNUSED,,3,,,,,,,,,
|
||||
C3,,DIFFM,IO_L02P_3,UNUSED,,3,,,,,,,,,
|
||||
C4,,DIFFS,IO_L10N_0,UNUSED,,0,,,,,,,,,
|
||||
C5,,DIFFS,IO_L09N_0,UNUSED,,0,,,,,,,,,
|
||||
C6,,DIFFS,IO_L08N_0/VREF_0,UNUSED,,0,,,,,,,,,
|
||||
C7,,,GND,,,,,,,,,,,,
|
||||
C8,,DIFFSI,IP_L06N_0/GCLK9,UNUSED,,0,,,,,,,,,
|
||||
C9,,DIFFS,IO_L04N_0/GCLK5,UNUSED,,0,,,,,,,,,
|
||||
C10,,,GND,,,,,,,,,,,,
|
||||
C11,,DIFFM,IO_L03P_0,UNUSED,,0,,,,,,,,,
|
||||
C12,,DIFFS,IO_L01N_0,UNUSED,,0,,,,,,,,,
|
||||
C13,,DIFFS,IO_L10N_1/LDC2,UNUSED,,1,,,,,,,,,
|
||||
C14,RGB<5>,IOB,IO_L10P_1/LDC1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
D1,,DIFFS,IO_L03N_3,UNUSED,,3,,,,,,,,,
|
||||
D2,,DIFFM,IO_L03P_3,UNUSED,,3,,,,,,,,,
|
||||
D3,,,VCCINT,,,,,,,,1.2,,,,
|
||||
D12,,DIFFS,IO_L09N_1/LDC0,UNUSED,,1,,,,,,,,,
|
||||
D13,RGB<6>,IOB,IO_L09P_1/HDC,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
D14,,,NC,,,,,,,,,,,,
|
||||
E1,,,VCCO_3,,,3,,,,,2.50,,,,
|
||||
E2,,IBUF,IP/VREF_3,UNUSED,,3,,,,,,,,,
|
||||
E3,,,GND,,,,,,,,,,,,
|
||||
E12,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
E13,,,VCCO_1,,,1,,,,,3.30,,,,
|
||||
E14,,,GND,,,,,,,,,,,,
|
||||
F1,,DIFFM,IO_L05P_3/LHCLK2,UNUSED,,3,,,,,,,,,
|
||||
F2,,DIFFS,IO_L04N_3/LHCLK1,UNUSED,,3,,,,,,,,,
|
||||
F3,,DIFFM,IO_L04P_3/LHCLK0,UNUSED,,3,,,,,,,,,
|
||||
F12,,DIFFS,IO/A0,UNUSED,,1,,,,,,,,,
|
||||
F13,RGB<7>,IOB,IO_L08N_1/A1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
F14,RGB<2>,IOB,IO_L08P_1/A2,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
G1,LED<7>,IOB,IO_L05N_3/LHCLK3/IRDY2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
G2,,,GND,,,,,,,,,,,,
|
||||
G3,,DIFFM,IO_L06P_3/LHCLK4/TRDY2,UNUSED,,3,,,,,,,,,
|
||||
G12,,IBUF,IP/VREF_1,UNUSED,,1,,,,,,,,,
|
||||
G13,RGB<3>,IOB,IO_L07N_1/A3/RHCLK7,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
G14,RGB<4>,IOB,IO_L07P_1/A4/RHCLK6,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
H1,,DIFFS,IO_L06N_3/LHCLK5,UNUSED,,3,,,,,,,,,
|
||||
H2,,DIFFM,IO_L07P_3/LHCLK6,UNUSED,,3,,,,,,,,,
|
||||
H3,,DIFFS,IO_L07N_3/LHCLK7,UNUSED,,3,,,,,,,,,
|
||||
H12,,DIFFS,IO_L06N_1/A5/RHCLK5,UNUSED,,1,,,,,,,,,
|
||||
H13,RGB<0>,IOB,IO_L06P_1/A6/RHCLK4/IRDY1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
H14,,,GND,,,,,,,,,,,,
|
||||
J1,,,GND,,,,,,,,,,,,
|
||||
J2,,,VCCO_3,,,3,,,,,2.50,,,,
|
||||
J3,,DIFFS,IO,UNUSED,,3,,,,,,,,,
|
||||
J12,,DIFFS,IO_L04N_1/A9/RHCLK1,UNUSED,,1,,,,,,,,,
|
||||
J13,RGB<1>,IOB,IO_L05P_1/A8/RHCLK2,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
J14,HS,IOB,IO_L05N_1/A7/RHCLK3/TRDY1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
K1,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
K2,,,NC,,,,,,,,,,,,
|
||||
K3,,IOB,IO/VREF_3,UNUSED,,3,,,,,,,,,
|
||||
K12,,,GND,,,,,,,,,,,,
|
||||
K13,VS,IOB,IO/VREF_1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE,
|
||||
K14,,DIFFM,IO_L04P_1/A10/RHCLK0,UNUSED,,1,,,,,,,,,
|
||||
L1,,DIFFM,IO_L08P_3,UNUSED,,3,,,,,,,,,
|
||||
L2,,DIFFS,IO_L08N_3,UNUSED,,3,,,,,,,,,
|
||||
L3,,DIFFM,IO_L09P_3,UNUSED,,3,,,,,,,,,
|
||||
L12,,,VCCINT,,,,,,,,1.2,,,,
|
||||
L13,,DIFFM,IO_L03P_1/A12,UNUSED,,1,,,,,,,,,
|
||||
L14,,DIFFS,IO_L03N_1/A11,UNUSED,,1,,,,,,,,,
|
||||
M1,,DIFFS,IO_L09N_3,UNUSED,,3,,,,,,,,,
|
||||
M2,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,,
|
||||
M3,,,GND,,,,,,,,,,,,
|
||||
M4,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,,
|
||||
M5,LED<0>,IOB,IO_L04P_2/D4/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
M6,CLK,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE,
|
||||
M7,,,GND,,,,,,,,,,,,
|
||||
M8,,,VCCO_2,,,2,,,,,2.50,,,,
|
||||
M9,,DIFFS,IO_L08N_2/A22,UNUSED,,2,,,,,,,,,
|
||||
M10,,DIFFS,IO_L09N_2/A20,UNUSED,,2,,,,,,,,,
|
||||
M11,LED<1>,IOB,IO_L10N_2/VS1/A18,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
M12,,DIFFM,IO_L02P_1/A14,UNUSED,,1,,,,,,,,,
|
||||
M13,,DIFFS,IO_L02N_1/A13,UNUSED,,1,,,,,,,,,
|
||||
M14,,,VCCO_1,,,1,,,,,3.30,,,,
|
||||
N1,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,,
|
||||
N2,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,,
|
||||
N3,,DIFFSI,IP/VREF_2,UNUSED,,2,,,,,,,,,
|
||||
N4,LED<5>,IOB,IO_L03N_2/D6/GCLK13,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
N5,LED<4>,IOB,IO_L04N_2/D3/GCLK15,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
N6,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,,
|
||||
N7,,IOB,IO/M1,UNUSED,,2,,,,,,,,,
|
||||
N8,,DIFFS,IO_L07N_2/DIN/D0,UNUSED,,2,,,,,,,,,
|
||||
N9,,DIFFM,IO_L08P_2/A23,UNUSED,,2,,,,,,,,,
|
||||
N10,,DIFFM,IO_L09P_2/A21,UNUSED,,2,,,,,,,,,
|
||||
N11,,DIFFM,IO_L10P_2/VS2/A19,UNUSED,,2,,,,,,,,,
|
||||
N12,,DIFFS,IO_L11N_2/CCLK,UNUSED,,2,,,,,,,,,
|
||||
N13,,DIFFM,IO_L01P_1/A16,UNUSED,,1,,,,,,,,,
|
||||
N14,,DIFFS,IO_L01N_1/A15,UNUSED,,1,,,,,,,,,
|
||||
P1,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,,
|
||||
P2,,,VCCINT,,,,,,,,1.2,,,,
|
||||
P3,,,VCCO_2,,,2,,,,,2.50,,,,
|
||||
P4,LED<6>,IOB,IO/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P5,,,GND,,,,,,,,,,,,
|
||||
P6,LED<3>,IOB,IO_L06P_2/D2/GCLK2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P7,LED<2>,IOB,IO_L06N_2/D1/GCLK3,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE,
|
||||
P8,,DIFFM,IO_L07P_2/M0,UNUSED,,2,,,,,,,,,
|
||||
P9,,,VCCAUX,,,,,,,,2.5,,,,
|
||||
P10,,,GND,,,,,,,,,,,,
|
||||
P11,,IOB,IO/VREF_2,UNUSED,,2,,,,,,,,,
|
||||
P12,,DIFFM,IO_L11P_2/VS0/A17,UNUSED,,2,,,,,,,,,
|
||||
P13,,,DONE,,,,,,,,,,,,
|
||||
P14,,,GND,,,,,,,,,,,,
|
||||
|
||||
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
|
||||
#
|
||||
#* Default value.
|
||||
#** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
#****** Special VCCO requirements may apply. Please consult the device
|
||||
# family datasheet for specific guideline on VCCO requirements.
|
||||
#
|
||||
#
|
||||
#
|
||||
|
162
main_pad.txt
Normal file
162
main_pad.txt
Normal file
|
|
@ -0,0 +1,162 @@
|
|||
Release 14.1 - par P.15xf (nt)
|
||||
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
|
||||
|
||||
Thu Feb 21 20:21:23 2013
|
||||
|
||||
|
||||
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
|
||||
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
|
||||
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
|
||||
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
|
||||
|
||||
INPUT FILE: main_map.ncd
|
||||
OUTPUT FILE: main_pad.txt
|
||||
PART TYPE: xc3s250e
|
||||
SPEED GRADE: -5
|
||||
PACKAGE: cp132
|
||||
|
||||
Pinout by Pin Number:
|
||||
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|A1 | | |PROG_B | | | | | | | | | | | |
|
||||
|A2 | | |TDI | | | | | | | | | | | |
|
||||
|A3 | |DIFFM |IO_L11P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A4 | | |GND | | | | | | | | | | | |
|
||||
|A5 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|A6 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|A7 | |DIFFM |IO_L07P_0/GCLK10 |UNUSED | |0 | | | | | | | | |
|
||||
|A8 | | |GND | | | | | | | | | | | |
|
||||
|A9 | |DIFFS |IO_L05N_0/GCLK7 |UNUSED | |0 | | | | | | | | |
|
||||
|A10 | |DIFFM |IO_L04P_0/GCLK4 |UNUSED | |0 | | | | | | | | |
|
||||
|A11 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|A12 | |DIFFS |IO_L02N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|A14 | | |TDO | | | | | | | | | | | |
|
||||
|B1 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | |
|
||||
|B4 | |DIFFM |IO_L10P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B6 | |DIFFM |IO_L08P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B7 | |DIFFS |IO_L07N_0/GCLK11 |UNUSED | |0 | | | | | | | | |
|
||||
|B8 | |DIFFMI |IP_L06P_0/GCLK8 |UNUSED | |0 | | | | | | | | |
|
||||
|B9 | |DIFFM |IO_L05P_0/GCLK6 |UNUSED | |0 | | | | | | | | |
|
||||
|B10 | | |VCCO_0 | | |0 | | | | |any******| | | |
|
||||
|B11 | |DIFFS |IO_L03N_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B12 | |DIFFM |IO_L02P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|B13 | | |TCK | | | | | | | | | | | |
|
||||
|B14 | | |TMS | | | | | | | | | | | |
|
||||
|C1 | | |GND | | | | | | | | | | | |
|
||||
|C2 | |DIFFS |IO_L02N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C3 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|C4 | |DIFFS |IO_L10N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C5 | |DIFFS |IO_L09N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C6 | |DIFFS |IO_L08N_0/VREF_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C7 | | |GND | | | | | | | | | | | |
|
||||
|C8 | |DIFFSI |IP_L06N_0/GCLK9 |UNUSED | |0 | | | | | | | | |
|
||||
|C9 | |DIFFS |IO_L04N_0/GCLK5 |UNUSED | |0 | | | | | | | | |
|
||||
|C10 | | |GND | | | | | | | | | | | |
|
||||
|C11 | |DIFFM |IO_L03P_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C12 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | |
|
||||
|C13 | |DIFFS |IO_L10N_1/LDC2 |UNUSED | |1 | | | | | | | | |
|
||||
|C14 |RGB<5> |IOB |IO_L10P_1/LDC1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|D1 | |DIFFS |IO_L03N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D2 | |DIFFM |IO_L03P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|D3 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|D12 | |DIFFS |IO_L09N_1/LDC0 |UNUSED | |1 | | | | | | | | |
|
||||
|D13 |RGB<6> |IOB |IO_L09P_1/HDC |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|D14 | | |NC | | | | | | | | | | | |
|
||||
|E1 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|
||||
|E2 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|E3 | | |GND | | | | | | | | | | | |
|
||||
|E12 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|E13 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|
||||
|E14 | | |GND | | | | | | | | | | | |
|
||||
|F1 | |DIFFM |IO_L05P_3/LHCLK2 |UNUSED | |3 | | | | | | | | |
|
||||
|F2 | |DIFFS |IO_L04N_3/LHCLK1 |UNUSED | |3 | | | | | | | | |
|
||||
|F3 | |DIFFM |IO_L04P_3/LHCLK0 |UNUSED | |3 | | | | | | | | |
|
||||
|F12 | |DIFFS |IO/A0 |UNUSED | |1 | | | | | | | | |
|
||||
|F13 |RGB<7> |IOB |IO_L08N_1/A1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|F14 |RGB<2> |IOB |IO_L08P_1/A2 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|G1 |LED<7> |IOB |IO_L05N_3/LHCLK3/IRDY2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|G2 | | |GND | | | | | | | | | | | |
|
||||
|G3 | |DIFFM |IO_L06P_3/LHCLK4/TRDY2 |UNUSED | |3 | | | | | | | | |
|
||||
|G12 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | |
|
||||
|G13 |RGB<3> |IOB |IO_L07N_1/A3/RHCLK7 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|G14 |RGB<4> |IOB |IO_L07P_1/A4/RHCLK6 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|H1 | |DIFFS |IO_L06N_3/LHCLK5 |UNUSED | |3 | | | | | | | | |
|
||||
|H2 | |DIFFM |IO_L07P_3/LHCLK6 |UNUSED | |3 | | | | | | | | |
|
||||
|H3 | |DIFFS |IO_L07N_3/LHCLK7 |UNUSED | |3 | | | | | | | | |
|
||||
|H12 | |DIFFS |IO_L06N_1/A5/RHCLK5 |UNUSED | |1 | | | | | | | | |
|
||||
|H13 |RGB<0> |IOB |IO_L06P_1/A6/RHCLK4/IRDY1|OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|H14 | | |GND | | | | | | | | | | | |
|
||||
|J1 | | |GND | | | | | | | | | | | |
|
||||
|J2 | | |VCCO_3 | | |3 | | | | |2.50 | | | |
|
||||
|J3 | |DIFFS |IO |UNUSED | |3 | | | | | | | | |
|
||||
|J12 | |DIFFS |IO_L04N_1/A9/RHCLK1 |UNUSED | |1 | | | | | | | | |
|
||||
|J13 |RGB<1> |IOB |IO_L05P_1/A8/RHCLK2 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|J14 |HS |IOB |IO_L05N_1/A7/RHCLK3/TRDY1|OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|K1 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|K2 | | |NC | | | | | | | | | | | |
|
||||
|K3 | |IOB |IO/VREF_3 |UNUSED | |3 | | | | | | | | |
|
||||
|K12 | | |GND | | | | | | | | | | | |
|
||||
|K13 |VS |IOB |IO/VREF_1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE |
|
||||
|K14 | |DIFFM |IO_L04P_1/A10/RHCLK0 |UNUSED | |1 | | | | | | | | |
|
||||
|L1 | |DIFFM |IO_L08P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L2 | |DIFFS |IO_L08N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L3 | |DIFFM |IO_L09P_3 |UNUSED | |3 | | | | | | | | |
|
||||
|L12 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|L13 | |DIFFM |IO_L03P_1/A12 |UNUSED | |1 | | | | | | | | |
|
||||
|L14 | |DIFFS |IO_L03N_1/A11 |UNUSED | |1 | | | | | | | | |
|
||||
|M1 | |DIFFS |IO_L09N_3 |UNUSED | |3 | | | | | | | | |
|
||||
|M2 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | |
|
||||
|M3 | | |GND | | | | | | | | | | | |
|
||||
|M4 | |DIFFM |IO_L03P_2/D7/GCLK12 |UNUSED | |2 | | | | | | | | |
|
||||
|M5 |LED<0> |IOB |IO_L04P_2/D4/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|M6 |CLK |IBUF |IP_L05P_2/RDWR_B/GCLK0 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE |
|
||||
|M7 | | |GND | | | | | | | | | | | |
|
||||
|M8 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|
||||
|M9 | |DIFFS |IO_L08N_2/A22 |UNUSED | |2 | | | | | | | | |
|
||||
|M10 | |DIFFS |IO_L09N_2/A20 |UNUSED | |2 | | | | | | | | |
|
||||
|M11 |LED<1> |IOB |IO_L10N_2/VS1/A18 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|M12 | |DIFFM |IO_L02P_1/A14 |UNUSED | |1 | | | | | | | | |
|
||||
|M13 | |DIFFS |IO_L02N_1/A13 |UNUSED | |1 | | | | | | | | |
|
||||
|M14 | | |VCCO_1 | | |1 | | | | |3.30 | | | |
|
||||
|N1 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | |
|
||||
|N2 | |DIFFS |IO_L02N_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | |
|
||||
|N3 | |DIFFSI |IP/VREF_2 |UNUSED | |2 | | | | | | | | |
|
||||
|N4 |LED<5> |IOB |IO_L03N_2/D6/GCLK13 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|N5 |LED<4> |IOB |IO_L04N_2/D3/GCLK15 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|N6 | |DIFFSI |IP_L05N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | |
|
||||
|N7 | |IOB |IO/M1 |UNUSED | |2 | | | | | | | | |
|
||||
|N8 | |DIFFS |IO_L07N_2/DIN/D0 |UNUSED | |2 | | | | | | | | |
|
||||
|N9 | |DIFFM |IO_L08P_2/A23 |UNUSED | |2 | | | | | | | | |
|
||||
|N10 | |DIFFM |IO_L09P_2/A21 |UNUSED | |2 | | | | | | | | |
|
||||
|N11 | |DIFFM |IO_L10P_2/VS2/A19 |UNUSED | |2 | | | | | | | | |
|
||||
|N12 | |DIFFS |IO_L11N_2/CCLK |UNUSED | |2 | | | | | | | | |
|
||||
|N13 | |DIFFM |IO_L01P_1/A16 |UNUSED | |1 | | | | | | | | |
|
||||
|N14 | |DIFFS |IO_L01N_1/A15 |UNUSED | |1 | | | | | | | | |
|
||||
|P1 | |DIFFM |IO_L02P_2/DOUT/BUSY |UNUSED | |2 | | | | | | | | |
|
||||
|P2 | | |VCCINT | | | | | | | |1.2 | | | |
|
||||
|P3 | | |VCCO_2 | | |2 | | | | |2.50 | | | |
|
||||
|P4 |LED<6> |IOB |IO/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P5 | | |GND | | | | | | | | | | | |
|
||||
|P6 |LED<3> |IOB |IO_L06P_2/D2/GCLK2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P7 |LED<2> |IOB |IO_L06N_2/D1/GCLK3 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|
||||
|P8 | |DIFFM |IO_L07P_2/M0 |UNUSED | |2 | | | | | | | | |
|
||||
|P9 | | |VCCAUX | | | | | | | |2.5 | | | |
|
||||
|P10 | | |GND | | | | | | | | | | | |
|
||||
|P11 | |IOB |IO/VREF_2 |UNUSED | |2 | | | | | | | | |
|
||||
|P12 | |DIFFM |IO_L11P_2/VS0/A17 |UNUSED | |2 | | | | | | | | |
|
||||
|P13 | | |DONE | | | | | | | | | | | |
|
||||
|P14 | | |GND | | | | | | | | | | | |
|
||||
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
* Default value.
|
||||
** This default Pullup/Pulldown value can be overridden in Bitgen.
|
||||
****** Special VCCO requirements may apply. Please consult the device
|
||||
family datasheet for specific guideline on VCCO requirements.
|
||||
|
||||
|
||||
1119
main_par.xrpt
Normal file
1119
main_par.xrpt
Normal file
File diff suppressed because it is too large
Load diff
189
main_summary.html
Normal file
189
main_summary.html
Normal file
|
|
@ -0,0 +1,189 @@
|
|||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (02/21/2013 - 20:21:36)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>pong.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>main</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Programming File Generated</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc3s250e-5cp132</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.1</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/*.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/fpga/pong\main.unroutes'>All Signals Completely Routed</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/fpga/pong\main.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/fpga/pong\main_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD>0 <A HREF_DISABLED='C:/fpga/pong\main.twx?&DataKey=XmlTimingReport'>(Timing Report)</A></TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='5'><B>Device Utilization Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number Slice Registers</TD>
|
||||
<TD ALIGN=RIGHT>47</TD>
|
||||
<TD ALIGN=RIGHT>4,896</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Flip Flops</TD>
|
||||
<TD ALIGN=RIGHT>45</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as Latches</TD>
|
||||
<TD ALIGN=RIGHT>2</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
|
||||
<TD ALIGN=RIGHT>58</TD>
|
||||
<TD ALIGN=RIGHT>4,896</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
|
||||
<TD ALIGN=RIGHT>52</TD>
|
||||
<TD ALIGN=RIGHT>2,448</TD>
|
||||
<TD ALIGN=RIGHT>2%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing only related logic</TD>
|
||||
<TD ALIGN=RIGHT>52</TD>
|
||||
<TD ALIGN=RIGHT>52</TD>
|
||||
<TD ALIGN=RIGHT>100%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number of Slices containing unrelated logic</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>52</TD>
|
||||
<TD ALIGN=RIGHT>0%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD>
|
||||
<TD ALIGN=RIGHT>92</TD>
|
||||
<TD ALIGN=RIGHT>4,896</TD>
|
||||
<TD ALIGN=RIGHT>1%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as logic</TD>
|
||||
<TD ALIGN=RIGHT>58</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT> Number used as a route-thru</TD>
|
||||
<TD ALIGN=RIGHT>34</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded <A HREF_DISABLED='C:/fpga/pong\main_map.xrpt?&DataKey=IOBProperties'>IOBs</A></TD>
|
||||
<TD ALIGN=RIGHT>19</TD>
|
||||
<TD ALIGN=RIGHT>92</TD>
|
||||
<TD ALIGN=RIGHT>20%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
|
||||
<TD ALIGN=RIGHT>1</TD>
|
||||
<TD ALIGN=RIGHT>24</TD>
|
||||
<TD ALIGN=RIGHT>4%</TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
|
||||
<TD ALIGN=RIGHT>2.67</TD>
|
||||
<TD> </TD>
|
||||
<TD> </TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Performance Summary</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=PerformanceSummary"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Final Timing Score:</B></TD>
|
||||
<TD>0 (Setup: 0, Hold: 0)</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Pinout Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\main_par.xrpt?&DataKey=PinoutData'>Pinout Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Routing Results:</B></TD><TD>
|
||||
<A HREF_DISABLED='C:/fpga/pong\main.unroutes'>All Signals Completely Routed</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Clock Data:</B></TD>
|
||||
<TD COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\main_par.xrpt?&DataKey=ClocksData'>Clock Report</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Timing Constraints:</B></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='C:/fpga/pong\main.ptwx?&DataKey=ConstraintsData'>All Constraints Met</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><B> </B></TD>
|
||||
<TD COLSPAN='2'> </TD>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:01 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:06 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:11 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/map.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:23 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:27 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:32 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Feb 21 20:21:32 2013</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Feb 21 20:21:36 2013</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 02/21/2013 - 20:21:36</center>
|
||||
</BODY></HTML>
|
||||
10
main_summary.xml
Normal file
10
main_summary.xml
Normal file
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DesignSummary rev="116">
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DesignSummary>
|
||||
452
main_usage.xml
Normal file
452
main_usage.xml
Normal file
|
|
@ -0,0 +1,452 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!-- IMPORTANT: This is an internal file that has been generated
|
||||
by the Xilinx ISE software. Any direct editing or
|
||||
changes made to this file may result in unpredictable
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<DeviceUsageSummary rev="116">
|
||||
<DesignStatistics TimeStamp="Thu Feb 21 20:21:32 2013"><group name="NetStatistics">
|
||||
<item name="NumNets_Active" rev="116">
|
||||
<attrib name="value" value="134"/></item>
|
||||
<item name="NumNets_Gnd" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNets_Vcc" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_CLKPIN" rev="116">
|
||||
<attrib name="value" value="27"/></item>
|
||||
<item name="NumNodesOfType_Active_CNTRLPIN" rev="116">
|
||||
<attrib name="value" value="29"/></item>
|
||||
<item name="NumNodesOfType_Active_DOUBLE" rev="116">
|
||||
<attrib name="value" value="151"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMY" rev="116">
|
||||
<attrib name="value" value="213"/></item>
|
||||
<item name="NumNodesOfType_Active_DUMMYESC" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_GLOBAL" rev="116">
|
||||
<attrib name="value" value="14"/></item>
|
||||
<item name="NumNodesOfType_Active_HFULLHEX" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_HUNIHEX" rev="116">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NumNodesOfType_Active_INPUT" rev="116">
|
||||
<attrib name="value" value="246"/></item>
|
||||
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_OMUX" rev="116">
|
||||
<attrib name="value" value="111"/></item>
|
||||
<item name="NumNodesOfType_Active_OUTPUT" rev="116">
|
||||
<attrib name="value" value="114"/></item>
|
||||
<item name="NumNodesOfType_Active_PREBXBY" rev="116">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="NumNodesOfType_Active_VFULLHEX" rev="116">
|
||||
<attrib name="value" value="7"/></item>
|
||||
<item name="NumNodesOfType_Active_VLONG" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NumNodesOfType_Active_VUNIHEX" rev="116">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<item name="NumNodesOfType_Gnd_DOUBLE" rev="116">
|
||||
<attrib name="value" value="10"/></item>
|
||||
<item name="NumNodesOfType_Gnd_INPUT" rev="116">
|
||||
<attrib name="value" value="12"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OMUX" rev="116">
|
||||
<attrib name="value" value="6"/></item>
|
||||
<item name="NumNodesOfType_Gnd_OUTPUT" rev="116">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="NumNodesOfType_Gnd_PREBXBY" rev="116">
|
||||
<attrib name="value" value="5"/></item>
|
||||
</group>
|
||||
<group name="MiscellaneousStatistics">
|
||||
<item name="AGG_BONDED_IO" rev="115">
|
||||
<attrib name="value" value="19"/></item>
|
||||
<item name="AGG_IO" rev="115">
|
||||
<attrib name="value" value="19"/></item>
|
||||
<item name="AGG_SLICE" rev="115">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="NUM_4_INPUT_LUT" rev="115">
|
||||
<attrib name="value" value="92"/></item>
|
||||
<item name="NUM_BONDED_IBUF" rev="115">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_BONDED_IOB" rev="115">
|
||||
<attrib name="value" value="18"/></item>
|
||||
<item name="NUM_BUFGMUX" rev="115">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="NUM_CYMUX" rev="115">
|
||||
<attrib name="value" value="45"/></item>
|
||||
<item name="NUM_LUT_RT" rev="115">
|
||||
<attrib name="value" value="34"/></item>
|
||||
<item name="NUM_SLICEL" rev="115">
|
||||
<attrib name="value" value="52"/></item>
|
||||
<item name="NUM_SLICE_FF" rev="115">
|
||||
<attrib name="value" value="45"/></item>
|
||||
<item name="NUM_SLICE_LATCH" rev="115">
|
||||
<attrib name="value" value="2"/></item>
|
||||
<item name="NUM_XOR" rev="115">
|
||||
<attrib name="value" value="50"/></item>
|
||||
</group>
|
||||
<group name="SiteStatistics">
|
||||
<item name="IBUF-DIFFMI" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="IOB-DIFFM" rev="116">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="IOB-DIFFS" rev="116">
|
||||
<attrib name="value" value="9"/></item>
|
||||
<item name="SLICEL-SLICEM" rev="116">
|
||||
<attrib name="value" value="21"/></item>
|
||||
</group>
|
||||
</DesignStatistics>
|
||||
<DeviceUsage TimeStamp="Thu Feb 21 20:21:32 2013"><group name="SiteSummary">
|
||||
<item name="BUFGMUX" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="BUFGMUX_GCLKMUX" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="BUFGMUX_GCLK_BUFFER" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="IBUF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="IBUF_INBUF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="IBUF_PAD" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
|
||||
<item name="IOB" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
|
||||
<item name="IOB_OUTBUF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
|
||||
<item name="IOB_PAD" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
|
||||
<item name="SLICEL" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="52"/></item>
|
||||
<item name="SLICEL_C1VDD" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
|
||||
<item name="SLICEL_C2VDD" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
|
||||
<item name="SLICEL_CYMUXF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item>
|
||||
<item name="SLICEL_CYMUXG" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item>
|
||||
<item name="SLICEL_F" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="48"/></item>
|
||||
<item name="SLICEL_F5MUX" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item>
|
||||
<item name="SLICEL_FFX" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item>
|
||||
<item name="SLICEL_FFY" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item>
|
||||
<item name="SLICEL_G" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="44"/></item>
|
||||
<item name="SLICEL_GNDF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
|
||||
<item name="SLICEL_GNDG" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
|
||||
<item name="SLICEL_XORF" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item>
|
||||
<item name="SLICEL_XORG" rev="116">
|
||||
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item>
|
||||
</group>
|
||||
</DeviceUsage>
|
||||
<ReportConfigData TimeStamp="Thu Feb 21 20:21:32 2013"><group name="IBUF_PAD">
|
||||
<item name="IOATTRBOX" rev="116">
|
||||
<attrib name="LVCMOS25" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL">
|
||||
<item name="BX" rev="116">
|
||||
<attrib name="BX_INV" value="0"/><attrib name="BX" value="8"/></item>
|
||||
<item name="BY" rev="116">
|
||||
<attrib name="BY" value="3"/><attrib name="BY_INV" value="0"/></item>
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CIN" rev="116">
|
||||
<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="20"/></item>
|
||||
<item name="CLK" rev="116">
|
||||
<attrib name="CLK" value="25"/><attrib name="CLK_INV" value="2"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="SR" value="14"/><attrib name="SR_INV" value="0"/></item>
|
||||
</group>
|
||||
<group name="IOB_OUTBUF">
|
||||
<item name="IN" rev="116">
|
||||
<attrib name="IN_INV" value="0"/><attrib name="IN" value="18"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="0" value="25"/><attrib name="0_INV" value="0"/></item>
|
||||
<item name="1" rev="116">
|
||||
<attrib name="1_INV" value="0"/><attrib name="1" value="25"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXG">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="0" value="20"/><attrib name="0_INV" value="0"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLKMUX">
|
||||
<item name="DISABLE_ATTR" rev="116">
|
||||
<attrib name="LOW" value="1"/></item>
|
||||
<item name="S" rev="116">
|
||||
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFX">
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CK" rev="116">
|
||||
<attrib name="CK" value="21"/><attrib name="CK_INV" value="1"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="D" value="22"/><attrib name="D_INV" value="0"/></item>
|
||||
<item name="FFX_INIT_ATTR" rev="116">
|
||||
<attrib name="INIT0" value="22"/></item>
|
||||
<item name="FFX_SR_ATTR" rev="116">
|
||||
<attrib name="SRLOW" value="22"/></item>
|
||||
<item name="LATCH_OR_FF" rev="116">
|
||||
<attrib name="FF" value="21"/><attrib name="LATCH" value="1"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="SR" value="10"/><attrib name="SR_INV" value="0"/></item>
|
||||
<item name="SYNC_ATTR" rev="116">
|
||||
<attrib name="ASYNC" value="12"/><attrib name="SYNC" value="10"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORF">
|
||||
<item name="1" rev="116">
|
||||
<attrib name="1_INV" value="0"/><attrib name="1" value="25"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFY">
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item>
|
||||
<item name="CK" rev="116">
|
||||
<attrib name="CK" value="24"/><attrib name="CK_INV" value="1"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="D" value="25"/><attrib name="D_INV" value="0"/></item>
|
||||
<item name="FFY_INIT_ATTR" rev="116">
|
||||
<attrib name="INIT0" value="24"/><attrib name="INIT1" value="1"/></item>
|
||||
<item name="FFY_SR_ATTR" rev="116">
|
||||
<attrib name="SRLOW" value="24"/><attrib name="SRHIGH" value="1"/></item>
|
||||
<item name="LATCH_OR_FF" rev="116">
|
||||
<attrib name="FF" value="24"/><attrib name="LATCH" value="1"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="SR" value="14"/><attrib name="SR_INV" value="0"/></item>
|
||||
<item name="SYNC_ATTR" rev="116">
|
||||
<attrib name="ASYNC" value="11"/><attrib name="SYNC" value="14"/></item>
|
||||
</group>
|
||||
<group name="IOB_PAD">
|
||||
<item name="DRIVEATTRBOX" rev="116">
|
||||
<attrib name="8" value="10"/><attrib name="12" value="8"/></item>
|
||||
<item name="IOATTRBOX" rev="116">
|
||||
<attrib name="LVCMOS25" value="8"/><attrib name="LVCMOS33" value="10"/></item>
|
||||
<item name="SLEW" rev="116">
|
||||
<attrib name="SLOW" value="8"/><attrib name="FAST" value="10"/></item>
|
||||
</group>
|
||||
<group name="IOB">
|
||||
<item name="O1" rev="116">
|
||||
<attrib name="O1_INV" value="0"/><attrib name="O1" value="18"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX">
|
||||
<item name="S" rev="116">
|
||||
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F5MUX">
|
||||
<item name="S0" rev="116">
|
||||
<attrib name="S0" value="3"/><attrib name="S0_INV" value="0"/></item>
|
||||
</group>
|
||||
</ReportConfigData>
|
||||
<ReportPinData TimeStamp="Thu Feb 21 20:21:32 2013"><group name="IBUF_PAD">
|
||||
<item name="PAD" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="IBUF_INBUF">
|
||||
<item name="IN" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL">
|
||||
<item name="BX" rev="116">
|
||||
<attrib name="value" value="8"/></item>
|
||||
<item name="BY" rev="116">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="CIN" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="CLK" rev="116">
|
||||
<attrib name="value" value="27"/></item>
|
||||
<item name="COUT" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="F1" rev="116">
|
||||
<attrib name="value" value="46"/></item>
|
||||
<item name="F2" rev="116">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="F3" rev="116">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="F4" rev="116">
|
||||
<attrib name="value" value="19"/></item>
|
||||
<item name="G1" rev="116">
|
||||
<attrib name="value" value="44"/></item>
|
||||
<item name="G2" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="G3" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="G4" rev="116">
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="value" value="14"/></item>
|
||||
<item name="X" rev="116">
|
||||
<attrib name="value" value="26"/></item>
|
||||
<item name="XQ" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="Y" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="YQ" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
</group>
|
||||
<group name="IOB_OUTBUF">
|
||||
<item name="IN" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXF">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="S0" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_CYMUXG">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="S0" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLKMUX">
|
||||
<item name="I0" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="S" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_C1VDD">
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="7"/></item>
|
||||
</group>
|
||||
<group name="IBUF">
|
||||
<item name="I" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="PAD" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFX">
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="CK" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="Q" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="value" value="10"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORF">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="O" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_FFY">
|
||||
<item name="CE" rev="116">
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="CK" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="Q" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="SR" rev="116">
|
||||
<attrib name="value" value="14"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_XORG">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
<item name="O" rev="116">
|
||||
<attrib name="value" value="25"/></item>
|
||||
</group>
|
||||
<group name="IOB_PAD">
|
||||
<item name="PAD" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
</group>
|
||||
<group name="IOB">
|
||||
<item name="O1" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
<item name="PAD" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX">
|
||||
<item name="I0" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="O" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="S" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_C2VDD">
|
||||
<item name="1" rev="116">
|
||||
<attrib name="value" value="2"/></item>
|
||||
</group>
|
||||
<group name="BUFGMUX_GCLK_BUFFER">
|
||||
<item name="IN" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="1"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F">
|
||||
<item name="A1" rev="116">
|
||||
<attrib name="value" value="46"/></item>
|
||||
<item name="A2" rev="116">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="A3" rev="116">
|
||||
<attrib name="value" value="23"/></item>
|
||||
<item name="A4" rev="116">
|
||||
<attrib name="value" value="19"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="value" value="48"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_F5MUX">
|
||||
<item name="F" rev="116">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="G" rev="116">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="OUT" rev="116">
|
||||
<attrib name="value" value="3"/></item>
|
||||
<item name="S0" rev="116">
|
||||
<attrib name="value" value="3"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_G">
|
||||
<item name="A1" rev="116">
|
||||
<attrib name="value" value="44"/></item>
|
||||
<item name="A2" rev="116">
|
||||
<attrib name="value" value="22"/></item>
|
||||
<item name="A3" rev="116">
|
||||
<attrib name="value" value="20"/></item>
|
||||
<item name="A4" rev="116">
|
||||
<attrib name="value" value="15"/></item>
|
||||
<item name="D" rev="116">
|
||||
<attrib name="value" value="44"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_GNDF">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
</group>
|
||||
<group name="SLICEL_GNDG">
|
||||
<item name="0" rev="116">
|
||||
<attrib name="value" value="18"/></item>
|
||||
</group>
|
||||
</ReportPinData>
|
||||
<CmdHistory>
|
||||
</CmdHistory>
|
||||
</DeviceUsageSummary>
|
||||
2
main_vhdl.prj
Normal file
2
main_vhdl.prj
Normal file
|
|
@ -0,0 +1,2 @@
|
|||
vhdl work "C:\fpga\pong\vga.vhd"
|
||||
vhdl work "C:\fpga\pong\main.vhd"
|
||||
212
main_xst.xrpt
Normal file
212
main_xst.xrpt
Normal file
|
|
@ -0,0 +1,212 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
|
||||
<document OS="nt" product="ISE" version="14.1">
|
||||
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Thu Feb 21 20:20:55 2013">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
<column stringID="value"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="variable" value="Path"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\\lib\nt;C:\Xilinx\14.1\ISE_DS\ISE\\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\bin\nt;C:\Xilinx\14.1\ISE_DS\ISE\lib\nt;C:\Xilinx\Vivado\2012.1\bin;C:\Xilinx\14.1\ISE_DS\PlanAhead\bin;C:\Xilinx\14.1\ISE_DS\EDK\bin\nt;C:\Xilinx\14.1\ISE_DS\EDK\lib\nt;C:\Xilinx\14.1\ISE_DS\EDK\gnu\microblaze\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\powerpc-eabi\nt\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnuwin\bin;C:\Xilinx\14.1\ISE_DS\EDK\gnu\arm\nt\bin;C:\Xilinx\14.1\ISE_DS\common\bin\nt;C:\Xilinx\14.1\ISE_DS\common\lib\nt;C:\GTK\bin;C:\Program Files (x86)\NVIDIA Corporation\PhysX\Common;C:\windows\system32;C:\windows;C:\windows\System32\Wbem;C:\windows\System32\WindowsPowerShell\v1.0\;C:\Program Files (x86)\Java\jre6\bin;c:\Program Files (x86)\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\Tools\Binn\;c:\Program Files\Microsoft SQL Server\100\DTS\Binn\;C:\Program Files\TortoiseSVN\bin;C:\Program Files (x86)\ATI Technologies\ATI.ACE\Core-Static;C:\Program Files (x86)\VisualSVN\bin;C:\Program Files (x86)\QuickTime\QTSystem\;C:\Program Files\MATLAB\R2011a\runtime\win64;C:\Program Files\MATLAB\R2011a\bin;C:\PROGRA~1\TIEDUC~1\TI-83P~1\UTILS;C:\Program Files (x86)\Microsoft ASP.NET\ASP.NET Web Pages\v1.0\;C:\Program Files\Microsoft SQL Server\110\Tools\Binn\;C:\Program Files\Microsoft\Web Platform Installer\;C:\Program Files (x86)\Windows Kits\8.0\Windows Performance Toolkit\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin\;C:\Program Files\IVI Foundation\VISA\Win64\Bin\;C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;L:\fortran\g95\bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="PATHEXT"/>
|
||||
<item stringID="value" value=".COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE\"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="XILINX_DSP"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\ISE"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\EDK"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="C:\Xilinx\14.1\ISE_DS\PlanAhead"/>
|
||||
</row>
|
||||
<row stringID="row" value="6">
|
||||
<item stringID="variable" value="XILINX_VIVADO"/>
|
||||
<item stringID="value" value="C:\Xilinx\Vivado\2012.1"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="Microsoft Windows 7 , 64-bit"/>
|
||||
<item stringID="User_EnvOsrelease" value="major release (build 7600)"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="ALECO-PC"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i3 CPU 550 @ 3.20GHz"/>
|
||||
<item stringID="speed" value="3191 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="XST_OPTION_SUMMARY">
|
||||
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="main.prj"/>
|
||||
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
|
||||
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="main"/>
|
||||
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s250e-5-cp132"/>
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="main"/>
|
||||
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
<item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
|
||||
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
|
||||
<item DEFAULT="<>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="<>"/>
|
||||
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
|
||||
<item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
|
||||
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
|
||||
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
|
||||
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
|
||||
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
|
||||
<item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
|
||||
<item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
|
||||
<item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
|
||||
<item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
|
||||
<item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
|
||||
<item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
|
||||
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
|
||||
<item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
|
||||
<item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
|
||||
<item DEFAULT="24" label="-bufg" stringID="XST_BUFG" value="24"/>
|
||||
<item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
|
||||
<item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
|
||||
<item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
|
||||
<item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
|
||||
<item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
|
||||
<item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
|
||||
<item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
|
||||
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="2">
|
||||
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="6">
|
||||
<item dataType="int" stringID="XST_1BIT_REGISTER" value="3"/>
|
||||
<item dataType="int" stringID="XST_10BIT_REGISTER" value="2"/>
|
||||
<item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="12"></item>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
|
||||
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4">
|
||||
<item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
|
||||
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COUNTERS" value="2">
|
||||
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="31">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="31"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_COMPARATORS" value="12"></item>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORT">
|
||||
<item dataType="int" stringID="XST_REGISTERS" value="45">
|
||||
<item dataType="int" stringID="XST_FLIPFLOPS" value="45"/>
|
||||
</item>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_REPORT">
|
||||
<section stringID="XST_PARTITION_IMPLEMENTATION_STATUS">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REPORT">
|
||||
<section stringID="XST_FINAL_RESULTS">
|
||||
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="main.ngr"/>
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="main"/>
|
||||
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
|
||||
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
|
||||
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_STATISTICS">
|
||||
<item stringID="XST_IOS" value="19"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="189">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_INV" value="11"/>
|
||||
<item dataType="int" stringID="XST_LUT1" value="33"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT2L" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="6"/>
|
||||
<item dataType="int" stringID="XST_LUT3L" value="3"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="29"/>
|
||||
<item dataType="int" stringID="XST_LUT4D" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT4L" value="4"/>
|
||||
<item dataType="int" stringID="XST_MUXCY" value="45"/>
|
||||
<item dataType="int" stringID="XST_MUXF5" value="3"/>
|
||||
<item dataType="int" stringID="XST_VCC" value="1"/>
|
||||
<item dataType="int" stringID="XST_XORCY" value="50"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="47">
|
||||
<item dataType="int" stringID="XST_FD" value="1"/>
|
||||
<item dataType="int" stringID="XST_FDE" value="20"/>
|
||||
<item dataType="int" stringID="XST_FDR" value="13"/>
|
||||
<item dataType="int" stringID="XST_FDRE" value="10"/>
|
||||
<item dataType="int" stringID="XST_FDS" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1">
|
||||
<item dataType="int" stringID="XST_BUFGP" value="1"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="18">
|
||||
<item dataType="int" stringID="XST_OBUF" value="18"/>
|
||||
</item>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="3s250ecp132-5"/>
|
||||
<item AVAILABLE="2448" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="50"/>
|
||||
<item AVAILABLE="4896" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="47"/>
|
||||
<item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="89"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="19"/>
|
||||
<item AVAILABLE="92" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="19"/>
|
||||
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
<section stringID="XST_ERRORS_STATISTICS">
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/>
|
||||
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="5"/>
|
||||
</section>
|
||||
</application>
|
||||
|
||||
</document>
|
||||
0
mainpins.ucf
Normal file
0
mainpins.ucf
Normal file
24
pins.ucf
Normal file
24
pins.ucf
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
NET "CLK" LOC = "M6";
|
||||
|
||||
NET "LED<0>" LOC = "M5";
|
||||
NET "LED<1>" LOC = "M11";
|
||||
NET "LED<2>" LOC = "P7";
|
||||
NET "LED<3>" LOC = "P6";
|
||||
NET "LED<4>" LOC = "N5";
|
||||
NET "LED<5>" LOC = "N4";
|
||||
NET "LED<6>" LOC = "P4";
|
||||
NET "LED<7>" LOC = "G1";
|
||||
|
||||
NET "RGB<7>" LOC = "F13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "RGB<6>" LOC = "D13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "RGB<5>" LOC = "C14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
|
||||
NET "RGB<4>" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "RGB<3>" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "RGB<2>" LOC = "F14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
|
||||
NET "RGB<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "RGB<0>" LOC = "H13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
|
||||
NET "HS" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
NET "VS" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST;
|
||||
188
pong.gise
Normal file
188
pong.gise
Normal file
|
|
@ -0,0 +1,188 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<generated_project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- For tool use only. Do not edit. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- ProjectNavigator created generated project file. -->
|
||||
|
||||
<!-- For use in tracking generated file and other information -->
|
||||
|
||||
<!-- allowing preservation of process status. -->
|
||||
|
||||
<!-- -->
|
||||
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
<version xmlns="http://www.xilinx.com/XMLSchema">11.1</version>
|
||||
|
||||
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="pong.xise"/>
|
||||
|
||||
<files xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="main.bgn" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="main.bit" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="main.bld"/>
|
||||
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="main.cmd_log"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="main.drc" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="main.lso"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="main.ncd" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="main.ngc"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="main.ngd"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="main.ngr"/>
|
||||
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="main.pad"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="main.par" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="main.pcf" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="main.prj"/>
|
||||
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="main.ptwx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="main.stx"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="main.syr"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="main.twr" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="main.twx" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="main.unroutes" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="main.ut" xil_pn:subbranch="FPGAConfiguration"/>
|
||||
<file xil_pn:fileType="FILE_XPI" xil_pn:name="main.xpi"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="main.xst"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="main_envsettings.html"/>
|
||||
<file xil_pn:fileType="FILE_NCD" xil_pn:name="main_guide.ncd" xil_pn:origination="imported"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="main_map.map" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="main_map.mrp" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="main_map.ncd" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="main_map.ngm" xil_pn:subbranch="Map"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="main_map.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="main_ngdbuild.xrpt"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="main_pad.csv" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="main_pad.txt" xil_pn:subbranch="Par"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="main_par.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="main_summary.html"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="main_summary.xml"/>
|
||||
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="main_usage.xml"/>
|
||||
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="main_vhdl.prj"/>
|
||||
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="main_xst.xrpt"/>
|
||||
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
|
||||
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
|
||||
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
|
||||
</files>
|
||||
|
||||
<transforms xmlns="http://www.xilinx.com/XMLSchema">
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="2559432503912502324" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_regenerateCores" xil_pn:prop_ck="1394965614382069540" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_SubProjectAbstractToPreProxy" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_xawsTohdl" xil_pn:prop_ck="-8835636825843433038" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="5199527252397519575" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1360993547" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-2819498606956104594" xil_pn:start_ts="1360993547">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499662" xil_pn:in_ck="-4648858705064165949" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="6360702674415490423" xil_pn:start_ts="1361499654">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<status xil_pn:value="OutOfDateForOutputs"/>
|
||||
<status xil_pn:value="OutputChanged"/>
|
||||
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
|
||||
<outfile xil_pn:name="main.lso"/>
|
||||
<outfile xil_pn:name="main.ngc"/>
|
||||
<outfile xil_pn:name="main.ngr"/>
|
||||
<outfile xil_pn:name="main.prj"/>
|
||||
<outfile xil_pn:name="main.stx"/>
|
||||
<outfile xil_pn:name="main.syr"/>
|
||||
<outfile xil_pn:name="main.xst"/>
|
||||
<outfile xil_pn:name="main_vhdl.prj"/>
|
||||
<outfile xil_pn:name="main_xst.xrpt"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
<outfile xil_pn:name="xst"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361491391" xil_pn:in_ck="4913312808198" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5369975691955938141" xil_pn:start_ts="1361491391">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499667" xil_pn:in_ck="-5850685379755905679" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3050130075436025607" xil_pn:start_ts="1361499662">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_ngo"/>
|
||||
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
|
||||
<outfile xil_pn:name="main.bld"/>
|
||||
<outfile xil_pn:name="main.ngd"/>
|
||||
<outfile xil_pn:name="main_ngdbuild.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499672" xil_pn:in_ck="-5850683973347287438" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="113730145005983477" xil_pn:start_ts="1361499667">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
|
||||
<outfile xil_pn:name="main.pcf"/>
|
||||
<outfile xil_pn:name="main_map.map"/>
|
||||
<outfile xil_pn:name="main_map.mrp"/>
|
||||
<outfile xil_pn:name="main_map.ncd"/>
|
||||
<outfile xil_pn:name="main_map.ngm"/>
|
||||
<outfile xil_pn:name="main_map.xrpt"/>
|
||||
<outfile xil_pn:name="main_summary.xml"/>
|
||||
<outfile xil_pn:name="main_usage.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499688" xil_pn:in_ck="106600371240438923" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="3129755442398015208" xil_pn:start_ts="1361499672">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="WarningsGenerated"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
|
||||
<outfile xil_pn:name="main.ncd"/>
|
||||
<outfile xil_pn:name="main.pad"/>
|
||||
<outfile xil_pn:name="main.par"/>
|
||||
<outfile xil_pn:name="main.ptwx"/>
|
||||
<outfile xil_pn:name="main.unroutes"/>
|
||||
<outfile xil_pn:name="main.xpi"/>
|
||||
<outfile xil_pn:name="main_pad.csv"/>
|
||||
<outfile xil_pn:name="main_pad.txt"/>
|
||||
<outfile xil_pn:name="main_par.xrpt"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499696" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1361499688">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
|
||||
<outfile xil_pn:name="main.bgn"/>
|
||||
<outfile xil_pn:name="main.bit"/>
|
||||
<outfile xil_pn:name="main.drc"/>
|
||||
<outfile xil_pn:name="main.ut"/>
|
||||
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
|
||||
<outfile xil_pn:name="webtalk.log"/>
|
||||
<outfile xil_pn:name="webtalk_pn.xml"/>
|
||||
</transform>
|
||||
<transform xil_pn:end_ts="1361499688" xil_pn:in_ck="-5850869619284895250" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1361499685">
|
||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
|
||||
<outfile xil_pn:name="main.twr"/>
|
||||
<outfile xil_pn:name="main.twx"/>
|
||||
</transform>
|
||||
</transforms>
|
||||
|
||||
</generated_project>
|
||||
349
pong.xise
Normal file
349
pong.xise
Normal file
|
|
@ -0,0 +1,349 @@
|
|||
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
|
||||
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
|
||||
|
||||
<header>
|
||||
<!-- ISE source project file created by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- This file contains project source information including a list of -->
|
||||
<!-- project source files, project and process properties. This file, -->
|
||||
<!-- along with the project source files, is sufficient to open and -->
|
||||
<!-- implement in ISE Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
|
||||
</header>
|
||||
|
||||
<version xil_pn:ise_version="14.1" xil_pn:schema_version="2"/>
|
||||
|
||||
<files>
|
||||
<file xil_pn:name="vga.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
|
||||
</file>
|
||||
<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
|
||||
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
|
||||
</file>
|
||||
<file xil_pn:name="pins.ucf" xil_pn:type="FILE_UCF">
|
||||
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
|
||||
</file>
|
||||
</files>
|
||||
|
||||
<properties>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Bus Delimiter" xil_pn:value="<>" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (1)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s250e" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3E" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Post-Place & Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|main|Behavioral" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top File" xil_pn:value="main.vhd" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/main" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="24" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Place & Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Output File Name" xil_pn:value="main" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="cp132" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="main_map.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="main_timesim.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="main_synthesis.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="main_translate.v" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="Verilog" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target UCF File Name" xil_pn:value="pins.ucf" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
<!-- The following properties are for internal use only. These should not be modified.-->
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="pong" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3e" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2013-02-15T19:54:09" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7EC662CDC4744D03A066C93D40613B74" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings>
|
||||
<binding xil_pn:location="/main" xil_pn:name="pins.ucf"/>
|
||||
</bindings>
|
||||
|
||||
<libraries/>
|
||||
|
||||
<autoManagedFiles>
|
||||
<!-- The following files are identified by `include statements in verilog -->
|
||||
<!-- source files and are automatically managed by Project Navigator. -->
|
||||
<!-- -->
|
||||
<!-- Do not hand-edit this section, as it will be overwritten when the -->
|
||||
<!-- project is analyzed based on files automatically identified as -->
|
||||
<!-- include files. -->
|
||||
</autoManagedFiles>
|
||||
|
||||
</project>
|
||||
1105
usage_statistics_webtalk.html
Normal file
1105
usage_statistics_webtalk.html
Normal file
File diff suppressed because it is too large
Load diff
69
vga.vhd
Normal file
69
vga.vhd
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
use IEEE.STD_LOGIC_ARITH.ALL;
|
||||
use IEEE.STD_LOGIC_UNSIGNED.ALL;
|
||||
|
||||
entity vga is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
|
||||
IRGB : in std_logic_vector(7 downto 0);
|
||||
RGB : out std_logic_vector(7 downto 0);
|
||||
|
||||
W : out std_logic;
|
||||
X : out std_logic_vector(9 downto 0);
|
||||
Y : out std_logic_vector(9 downto 0);
|
||||
|
||||
HS : out std_logic;
|
||||
VS : out std_logic
|
||||
);
|
||||
end vga;
|
||||
|
||||
architecture Behavioral of vga is
|
||||
signal horiz : std_logic_vector(9 downto 0);
|
||||
signal vert : std_logic_vector(9 downto 0);
|
||||
begin
|
||||
|
||||
process (CLK) begin
|
||||
if CLK'event and CLK = '1' then
|
||||
-- 144 and 784
|
||||
if (horiz >= 146) and (horiz < 788)
|
||||
-- 39 and 519
|
||||
and (vert >= 32) and (vert < 519) then
|
||||
W <= '1';
|
||||
RGB <= IRGB;
|
||||
X <= horiz - 144 + 1;
|
||||
Y <= vert - 39 + 1;
|
||||
else
|
||||
W <= '0';
|
||||
RGB <= "11100011";
|
||||
end if;
|
||||
|
||||
if (horiz > 0) and (horiz < 97) then
|
||||
HS <= '0';
|
||||
else
|
||||
HS <= '1';
|
||||
end if;
|
||||
|
||||
if (vert > 0) and (vert < 3) then
|
||||
VS <= '0';
|
||||
else
|
||||
VS <= '1';
|
||||
end if;
|
||||
|
||||
horiz <= horiz + 1;
|
||||
if (horiz = 800) then
|
||||
vert <= vert + 1;
|
||||
horiz <= (others => '0');
|
||||
end if;
|
||||
|
||||
if (vert = 521) then
|
||||
vert <= (others => '0');
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
end Behavioral;
|
||||
|
||||
82
vga_summary.html
Normal file
82
vga_summary.html
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (02/16/2013 - 01:50:51)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>pong.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>vga</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Programming File Not Generated</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc3s250e-5cp132</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.1</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD> </TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Synthesis Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>CPLD Fitter Report (Text)</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Sat Feb 16 01:50:46 2013</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Sat Feb 16 01:50:50 2013</TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 02/16/2013 - 01:50:51</center>
|
||||
</BODY></HTML>
|
||||
0
vgapins.ucf
Normal file
0
vgapins.ucf
Normal file
45
webtalk_pn.xml
Normal file
45
webtalk_pn.xml
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
<?xml version="1.0" encoding="UTF-8" ?>
|
||||
<document>
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Thu Feb 21 20:21:12 2013">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="project"/>
|
||||
<property name="ProjectIteration" value="58" type="project"/>
|
||||
<property name="ProjectFile" value="C:/fpga/pong/pong.xise" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="2013-02-15T19:54:09" type="project"/>
|
||||
</section>
|
||||
<section name="Project Statistics" visible="true">
|
||||
<property name="PROPEXT_xilxSynthMaxFanout_virtex2" value="100000" type="process"/>
|
||||
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
|
||||
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
|
||||
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
|
||||
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
|
||||
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
|
||||
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
|
||||
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
|
||||
<property name="PROP_SynthTopFile" value="changed" type="process"/>
|
||||
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
|
||||
<property name="PROP_UseSmartGuide" value="false" type="design"/>
|
||||
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="2013-02-15T19:54:09" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="design"/>
|
||||
<property name="PROP_intWbtProjectIteration" value="58" type="process"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
|
||||
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
|
||||
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
|
||||
<property name="PROP_AutoTop" value="false" type="design"/>
|
||||
<property name="PROP_DevFamily" value="Spartan3E" type="design"/>
|
||||
<property name="PROP_DevDevice" value="xc3s250e" type="design"/>
|
||||
<property name="PROP_DevFamilyPMName" value="spartan3e" type="design"/>
|
||||
<property name="PROP_DevPackage" value="cp132" type="design"/>
|
||||
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
|
||||
<property name="PROP_DevSpeed" value="-5" type="design"/>
|
||||
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
|
||||
<property name="FILE_UCF" value="1" type="source"/>
|
||||
<property name="FILE_VHDL" value="2" type="source"/>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
BIN
xlnx_auto_0_xdb/cst.xbcd
Normal file
BIN
xlnx_auto_0_xdb/cst.xbcd
Normal file
Binary file not shown.
4
xst/work/hdllib.ref
Normal file
4
xst/work/hdllib.ref
Normal file
|
|
@ -0,0 +1,4 @@
|
|||
AR vga behavioral C:/fpga/pong/vga.vhd sub00/vhpl03 1361499657
|
||||
AR main behavioral C:/fpga/pong/main.vhd sub00/vhpl01 1361499659
|
||||
EN main NULL C:/fpga/pong/main.vhd sub00/vhpl00 1361499658
|
||||
EN vga NULL C:/fpga/pong/vga.vhd sub00/vhpl02 1361499656
|
||||
11
xst/work/hdpdeps.ref
Normal file
11
xst/work/hdpdeps.ref
Normal file
|
|
@ -0,0 +1,11 @@
|
|||
V3 7
|
||||
FL C:/fpga/pong/main.vhd 2013/02/21.18:24:26 P.15xf
|
||||
EN work/main 1361499658 FL C:/fpga/pong/main.vhd PB ieee/std_logic_1164 1335251622 \
|
||||
PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625
|
||||
AR work/main/Behavioral 1361499659 \
|
||||
FL C:/fpga/pong/main.vhd EN work/main 1361499658 CP vga
|
||||
FL C:/fpga/pong/vga.vhd 2013/02/21.20:20:49 P.15xf
|
||||
EN work/vga 1361499656 FL C:/fpga/pong/vga.vhd PB ieee/std_logic_1164 1335251622 \
|
||||
PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625
|
||||
AR work/vga/Behavioral 1361499657 \
|
||||
FL C:/fpga/pong/vga.vhd EN work/vga 1361499656
|
||||
BIN
xst/work/sub00/vhpl00.vho
Normal file
BIN
xst/work/sub00/vhpl00.vho
Normal file
Binary file not shown.
BIN
xst/work/sub00/vhpl01.vho
Normal file
BIN
xst/work/sub00/vhpl01.vho
Normal file
Binary file not shown.
BIN
xst/work/sub00/vhpl02.vho
Normal file
BIN
xst/work/sub00/vhpl02.vho
Normal file
Binary file not shown.
BIN
xst/work/sub00/vhpl03.vho
Normal file
BIN
xst/work/sub00/vhpl03.vho
Normal file
Binary file not shown.
Loading…
Reference in a new issue