commit ef1ee1e003caa926de7ddd67c1b937e6d27e3fe5 Author: Alec Obradovich Date: Thu Feb 21 20:27:53 2013 -0600 init diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..412eeda --- /dev/null +++ b/.gitattributes @@ -0,0 +1,22 @@ +# Auto detect text files and perform LF normalization +* text=auto + +# Custom for Visual Studio +*.cs diff=csharp +*.sln merge=union +*.csproj merge=union +*.vbproj merge=union +*.fsproj merge=union +*.dbproj merge=union + +# Standard to msysgit +*.doc diff=astextplain +*.DOC diff=astextplain +*.docx diff=astextplain +*.DOCX diff=astextplain +*.dot diff=astextplain +*.DOT diff=astextplain +*.pdf diff=astextplain +*.PDF diff=astextplain +*.rtf diff=astextplain +*.RTF diff=astextplain diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..b9d6bd9 --- /dev/null +++ b/.gitignore @@ -0,0 +1,215 @@ +################# +## Eclipse +################# + +*.pydevproject +.project +.metadata +bin/ +tmp/ +*.tmp +*.bak +*.swp +*~.nib +local.properties +.classpath +.settings/ +.loadpath + +# External tool builders +.externalToolBuilders/ + +# Locally stored "Eclipse launch configurations" +*.launch + +# CDT-specific +.cproject + +# PDT-specific +.buildpath + + +################# +## Visual Studio +################# + +## Ignore Visual Studio temporary files, build results, and +## files generated by popular Visual Studio add-ons. + +# User-specific files +*.suo +*.user +*.sln.docstates + +# Build results + +[Dd]ebug/ +[Rr]elease/ +x64/ +build/ +[Bb]in/ +[Oo]bj/ + +# MSTest test Results +[Tt]est[Rr]esult*/ +[Bb]uild[Ll]og.* + +*_i.c +*_p.c +*.ilk +*.meta +*.obj +*.pch +*.pdb +*.pgc +*.pgd +*.rsp +*.sbr +*.tlb +*.tli +*.tlh +*.tmp +*.tmp_proj +*.log +*.vspscc +*.vssscc +.builds +*.pidb +*.log +*.scc + +# Visual C++ cache files +ipch/ +*.aps +*.ncb +*.opensdf +*.sdf +*.cachefile + +# Visual Studio profiler +*.psess +*.vsp +*.vspx + +# Guidance Automation Toolkit +*.gpState + +# ReSharper is a .NET coding add-in +_ReSharper*/ +*.[Rr]e[Ss]harper + +# TeamCity is a build add-in +_TeamCity* + +# DotCover is a Code Coverage Tool +*.dotCover + +# NCrunch +*.ncrunch* +.*crunch*.local.xml + +# Installshield output folder +[Ee]xpress/ + +# DocProject is a documentation generator add-in +DocProject/buildhelp/ +DocProject/Help/*.HxT +DocProject/Help/*.HxC +DocProject/Help/*.hhc +DocProject/Help/*.hhk +DocProject/Help/*.hhp +DocProject/Help/Html2 +DocProject/Help/html + +# Click-Once directory +publish/ + +# Publish Web Output +*.Publish.xml +*.pubxml + +# NuGet Packages Directory +## TODO: If you have NuGet Package Restore enabled, uncomment the next line +#packages/ + +# Windows Azure Build Output +csx +*.build.csdef + +# Windows Store app package directory +AppPackages/ + +# Others +sql/ +*.Cache +ClientBin/ +[Ss]tyle[Cc]op.* +~$* +*~ +*.dbmdl +*.[Pp]ublish.xml +*.pfx +*.publishsettings + +# RIA/Silverlight projects +Generated_Code/ + +# Backup & report files from converting an old project file to a newer +# Visual Studio version. Backup files are not needed, because we have git ;-) +_UpgradeReport_Files/ +Backup*/ +UpgradeLog*.XML +UpgradeLog*.htm + +# SQL Server files +App_Data/*.mdf +App_Data/*.ldf + +############# +## Windows detritus +############# + +# Windows image file caches +Thumbs.db +ehthumbs.db + +# Folder config file +Desktop.ini + +# Recycle Bin used on file shares +$RECYCLE.BIN/ + +# Mac crap +.DS_Store + + +############# +## Python +############# + +*.py[co] + +# Packages +*.egg +*.egg-info +dist/ +build/ +eggs/ +parts/ +var/ +sdist/ +develop-eggs/ +.installed.cfg + +# Installer logs +pip-log.txt + +# Unit test / coverage reports +.coverage +.tox + +#Translations +*.mo + +#Mr Developer +.mr.developer.cfg diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst new file mode 100644 index 0000000..e9066cf --- /dev/null +++ b/_ngo/netlist.lst @@ -0,0 +1,2 @@ +C:\fpga\pong\main.ngc 1361499661 +OK diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/_xmsgs/bitgen.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs new file mode 100644 index 0000000..0e57921 --- /dev/null +++ b/_xmsgs/map.xmsgs @@ -0,0 +1,12 @@ + + + +No environment variables are currently set. + + + + diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs new file mode 100644 index 0000000..e1a4f3b --- /dev/null +++ b/_xmsgs/par.xmsgs @@ -0,0 +1,18 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + + +CLK Net:VGADriver/W may have excessive skew because + 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. + + +N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..e68a4d4 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "C:/fpga/pong/vga.vhd" into library work + + + + diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100644 index 0000000..d69208e --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,21 @@ + + + +No timing constraints found, doing default enumeration. + +To improve timing, see the Timing Closure User Guide (UG612). + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + +This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. + +This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..fc8925d --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,34 @@ + + + +"C:/fpga/pong/main.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: +<w>, <x>, <y> + + +Output <LED> is never assigned. Tied to value 00000000. + + +Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. + + +The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 4 FFs/Latches, which will be removed : <6> <5> <1> <0> + + +The FF/Latch <4> in Unit <LPM_LATCH_1> is equivalent to the following 2 FFs/Latches, which will be removed : <3> <2> + + +The FF/Latch <VGADriver/RGB_4> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <VGADriver/RGB_3> <VGADriver/RGB_2> + + +The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 4 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_1> <VGADriver/RGB_0> + + +HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + + + + diff --git a/clockadjust.vhd b/clockadjust.vhd new file mode 100644 index 0000000..bd934af --- /dev/null +++ b/clockadjust.vhd @@ -0,0 +1,14 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_1164.ALL; + +entity clockadjust is +end clockadjust; + +architecture Behavioral of clockadjust is + +begin + + +end Behavioral; + diff --git a/ggg.ucf b/ggg.ucf new file mode 100644 index 0000000..e69de29 diff --git a/iseconfig/main.xreport b/iseconfig/main.xreport new file mode 100644 index 0000000..c325d21 --- /dev/null +++ b/iseconfig/main.xreport @@ -0,0 +1,215 @@ + + +
+ 2013-02-18T14:32:38 + main + Unknown + C:/fpga/pong/iseconfig/main.xreport + C:/fpga/pong\ + 2013-02-15T20:59:38 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/iseconfig/pong.projectmgr b/iseconfig/pong.projectmgr new file mode 100644 index 0000000..aff3510 --- /dev/null +++ b/iseconfig/pong.projectmgr @@ -0,0 +1,95 @@ + + + + + + + + + 2 + + + main - Behavioral (C:/fpga/pong/main.vhd) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000123000000020000000000000000000000000200000064ffffffff000000810000000300000002000001230000000100000003000000000000000100000003 + true + main - Behavioral (C:/fpga/pong/main.vhd) + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000 + false + + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000126000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004200000001000000000000002400000001000000000000006600000001000000000000005a0000000100000000 + false + + + + + 1 + work + + + 0 + 0 + 000000ff000000000000000100000000000000000100000000000000000000000000000000000000f8000000010001000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 + false + work + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + User Constraints + + + Generate Programming File + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000 + false + Generate Programming File + + + + 1 + User Constraints + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f2000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f20000000100000000 + false + + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + diff --git a/main.bgn b/main.bgn new file mode 100644 index 0000000..9ceceb8 --- /dev/null +++ b/main.bgn @@ -0,0 +1,94 @@ +Release 14.1 - Bitgen P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +Loading device for application Rf_Device from file '3s250e.nph' in environment +C:\Xilinx\14.1\ISE_DS\ISE\. + "main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5 +Opened constraints file main.pcf. + +Thu Feb 21 20:21:30 2013 + +C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No main.ncd + +Summary of Bitgen Options: ++----------------------+----------------------+ +| Option Name | Current Setting | ++----------------------+----------------------+ +| Compress | (Not Specified)* | ++----------------------+----------------------+ +| Readback | (Not Specified)* | ++----------------------+----------------------+ +| CRC | Enable** | ++----------------------+----------------------+ +| DebugBitstream | No** | ++----------------------+----------------------+ +| ConfigRate | 1** | ++----------------------+----------------------+ +| StartupClk | Cclk** | ++----------------------+----------------------+ +| DCMShutdown | Disable** | ++----------------------+----------------------+ +| DonePin | Pullup** | ++----------------------+----------------------+ +| ProgPin | Pullup** | ++----------------------+----------------------+ +| TckPin | Pullup** | ++----------------------+----------------------+ +| TdiPin | Pullup** | ++----------------------+----------------------+ +| TdoPin | Pullup** | ++----------------------+----------------------+ +| TmsPin | Pullup** | ++----------------------+----------------------+ +| UnusedPin | Pulldown** | ++----------------------+----------------------+ +| GWE_cycle | 6** | ++----------------------+----------------------+ +| GTS_cycle | 5** | ++----------------------+----------------------+ +| LCK_cycle | NoWait** | ++----------------------+----------------------+ +| DONE_cycle | 4** | ++----------------------+----------------------+ +| Persist | No* | ++----------------------+----------------------+ +| DriveDone | No** | ++----------------------+----------------------+ +| DonePipe | Yes | ++----------------------+----------------------+ +| Security | None** | ++----------------------+----------------------+ +| UserID | 0xFFFFFFFF** | ++----------------------+----------------------+ +| MultiBootMode | No* | ++----------------------+----------------------+ +| ActivateGclk | No* | ++----------------------+----------------------+ +| ActiveReconfig | No* | ++----------------------+----------------------+ +| PartialMask0 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask1 | (Not Specified)* | ++----------------------+----------------------+ +| PartialMask2 | (Not Specified)* | ++----------------------+----------------------+ +| PartialGclk | (Not Specified)* | ++----------------------+----------------------+ +| PartialLeft | (Not Specified)* | ++----------------------+----------------------+ +| PartialRight | (Not Specified)* | ++----------------------+----------------------+ +| IEEE1532 | No* | ++----------------------+----------------------+ +| Binary | No** | ++----------------------+----------------------+ + * Default setting. + ** The specified setting matches the default setting. + +There were 0 CONFIG constraint(s) processed from main.pcf. + + +Running DRC. +DRC detected 0 errors and 0 warnings. +Creating bit map... +Saving bit stream in "main.bit". +Bitstream generation is complete. diff --git a/main.bit b/main.bit new file mode 100644 index 0000000..3e991a8 Binary files /dev/null and b/main.bit differ diff --git a/main.bld b/main.bld new file mode 100644 index 0000000..fb81aae --- /dev/null +++ b/main.bld @@ -0,0 +1,35 @@ +Release 14.1 ngdbuild P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Command Line: C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\ngdbuild.exe -intstyle +ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd + +Reading NGO file "C:/fpga/pong/main.ngc" ... +Gathering constraint information from source properties... +Done. + +Annotating constraints to design from ucf file "pins.ucf" ... +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 129668 kilobytes + +Writing NGD file "main.ngd" ... +Total REAL time to NGDBUILD completion: 3 sec +Total CPU time to NGDBUILD completion: 3 sec + +Writing NGDBUILD log file "main.bld"... diff --git a/main.cmd_log b/main.cmd_log new file mode 100644 index 0000000..d5c357c --- /dev/null +++ b/main.cmd_log @@ -0,0 +1,378 @@ +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn 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main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd +xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd +map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf +bitgen -intstyle ise -f main.ut main.ncd diff --git a/main.drc b/main.drc new file mode 100644 index 0000000..08567f5 --- /dev/null +++ b/main.drc @@ -0,0 +1,8 @@ +Release 14.1 Drc P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Thu Feb 21 20:21:30 2013 + +drc -z main.ncd main.pcf + +DRC detected 0 errors and 0 warnings. diff --git a/main.lso b/main.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/main.lso @@ -0,0 +1 @@ +work diff --git a/main.ncd b/main.ncd new file mode 100644 index 0000000..bda6523 --- /dev/null +++ b/main.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4424:XlxV32DM 3fff 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`2=9>80bh=55:p53e=838p1h65739>53g=j11/i94>739ma6<13ty::o4?:3y>a=<1n27::l4m7:&f0?70:2dn?794}|~yEFDs:lo68l;103`exFGJr:vLM^t}AB \ No newline at end of file diff --git a/main.pad b/main.pad new file mode 100644 index 0000000..2c5bee5 --- /dev/null +++ b/main.pad @@ -0,0 +1,162 @@ +Release 14.1 - par P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Thu Feb 21 20:21:23 2013 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: main_map.ncd +OUTPUT FILE: main.pad +PART TYPE: xc3s250e +SPEED GRADE: -5 +PACKAGE: cp132 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +A1|||PROG_B|||||||||||| +A2|||TDI|||||||||||| +A3||DIFFM|IO_L11P_0|UNUSED||0||||||||| +A4|||GND|||||||||||| +A5|||VCCAUX||||||||2.5|||| +A6|||VCCO_0|||0|||||any******|||| +A7||DIFFM|IO_L07P_0/GCLK10|UNUSED||0||||||||| +A8|||GND|||||||||||| +A9||DIFFS|IO_L05N_0/GCLK7|UNUSED||0||||||||| +A10||DIFFM|IO_L04P_0/GCLK4|UNUSED||0||||||||| +A11|||VCCINT||||||||1.2|||| +A12||DIFFS|IO_L02N_0|UNUSED||0||||||||| +A13||DIFFM|IO_L01P_0|UNUSED||0||||||||| +A14|||TDO|||||||||||| +B1||DIFFS|IO_L01N_3|UNUSED||3||||||||| +B2||DIFFM|IO_L01P_3|UNUSED||3||||||||| +B3||DIFFS|IO_L11N_0/HSWAP|UNUSED||0||||||||| +B4||DIFFM|IO_L10P_0|UNUSED||0||||||||| +B5||DIFFM|IO_L09P_0|UNUSED||0||||||||| +B6||DIFFM|IO_L08P_0|UNUSED||0||||||||| +B7||DIFFS|IO_L07N_0/GCLK11|UNUSED||0||||||||| +B8||DIFFMI|IP_L06P_0/GCLK8|UNUSED||0||||||||| +B9||DIFFM|IO_L05P_0/GCLK6|UNUSED||0||||||||| +B10|||VCCO_0|||0|||||any******|||| +B11||DIFFS|IO_L03N_0/VREF_0|UNUSED||0||||||||| +B12||DIFFM|IO_L02P_0|UNUSED||0||||||||| +B13|||TCK|||||||||||| +B14|||TMS|||||||||||| +C1|||GND|||||||||||| +C2||DIFFS|IO_L02N_3|UNUSED||3||||||||| +C3||DIFFM|IO_L02P_3|UNUSED||3||||||||| +C4||DIFFS|IO_L10N_0|UNUSED||0||||||||| +C5||DIFFS|IO_L09N_0|UNUSED||0||||||||| +C6||DIFFS|IO_L08N_0/VREF_0|UNUSED||0||||||||| +C7|||GND|||||||||||| +C8||DIFFSI|IP_L06N_0/GCLK9|UNUSED||0||||||||| +C9||DIFFS|IO_L04N_0/GCLK5|UNUSED||0||||||||| +C10|||GND|||||||||||| +C11||DIFFM|IO_L03P_0|UNUSED||0||||||||| +C12||DIFFS|IO_L01N_0|UNUSED||0||||||||| +C13||DIFFS|IO_L10N_1/LDC2|UNUSED||1||||||||| +C14|RGB<5>|IOB|IO_L10P_1/LDC1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +D1||DIFFS|IO_L03N_3|UNUSED||3||||||||| +D2||DIFFM|IO_L03P_3|UNUSED||3||||||||| +D3|||VCCINT||||||||1.2|||| +D12||DIFFS|IO_L09N_1/LDC0|UNUSED||1||||||||| +D13|RGB<6>|IOB|IO_L09P_1/HDC|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +D14|||NC|||||||||||| +E1|||VCCO_3|||3|||||2.50|||| +E2||IBUF|IP/VREF_3|UNUSED||3||||||||| +E3|||GND|||||||||||| +E12|||VCCAUX||||||||2.5|||| +E13|||VCCO_1|||1|||||3.30|||| +E14|||GND|||||||||||| +F1||DIFFM|IO_L05P_3/LHCLK2|UNUSED||3||||||||| +F2||DIFFS|IO_L04N_3/LHCLK1|UNUSED||3||||||||| +F3||DIFFM|IO_L04P_3/LHCLK0|UNUSED||3||||||||| +F12||DIFFS|IO/A0|UNUSED||1||||||||| +F13|RGB<7>|IOB|IO_L08N_1/A1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +F14|RGB<2>|IOB|IO_L08P_1/A2|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +G1|LED<7>|IOB|IO_L05N_3/LHCLK3/IRDY2|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE| +G2|||GND|||||||||||| +G3||DIFFM|IO_L06P_3/LHCLK4/TRDY2|UNUSED||3||||||||| +G12||IBUF|IP/VREF_1|UNUSED||1||||||||| +G13|RGB<3>|IOB|IO_L07N_1/A3/RHCLK7|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +G14|RGB<4>|IOB|IO_L07P_1/A4/RHCLK6|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +H1||DIFFS|IO_L06N_3/LHCLK5|UNUSED||3||||||||| +H2||DIFFM|IO_L07P_3/LHCLK6|UNUSED||3||||||||| +H3||DIFFS|IO_L07N_3/LHCLK7|UNUSED||3||||||||| +H12||DIFFS|IO_L06N_1/A5/RHCLK5|UNUSED||1||||||||| +H13|RGB<0>|IOB|IO_L06P_1/A6/RHCLK4/IRDY1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +H14|||GND|||||||||||| +J1|||GND|||||||||||| +J2|||VCCO_3|||3|||||2.50|||| +J3||DIFFS|IO|UNUSED||3||||||||| +J12||DIFFS|IO_L04N_1/A9/RHCLK1|UNUSED||1||||||||| +J13|RGB<1>|IOB|IO_L05P_1/A8/RHCLK2|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +J14|HS|IOB|IO_L05N_1/A7/RHCLK3/TRDY1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +K1|||VCCAUX||||||||2.5|||| +K2|||NC|||||||||||| +K3||IOB|IO/VREF_3|UNUSED||3||||||||| +K12|||GND|||||||||||| +K13|VS|IOB|IO/VREF_1|OUTPUT|LVCMOS33|1|8|FAST|NONE**|||LOCATED|NO|NONE| +K14||DIFFM|IO_L04P_1/A10/RHCLK0|UNUSED||1||||||||| +L1||DIFFM|IO_L08P_3|UNUSED||3||||||||| +L2||DIFFS|IO_L08N_3|UNUSED||3||||||||| +L3||DIFFM|IO_L09P_3|UNUSED||3||||||||| +L12|||VCCINT||||||||1.2|||| +L13||DIFFM|IO_L03P_1/A12|UNUSED||1||||||||| +L14||DIFFS|IO_L03N_1/A11|UNUSED||1||||||||| +M1||DIFFS|IO_L09N_3|UNUSED||3||||||||| +M2||DIFFM|IO_L01P_2/CSO_B|UNUSED||2||||||||| +M3|||GND|||||||||||| +M4||DIFFM|IO_L03P_2/D7/GCLK12|UNUSED||2||||||||| +M5|LED<0>|IOB|IO_L04P_2/D4/GCLK14|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +M6|CLK|IBUF|IP_L05P_2/RDWR_B/GCLK0|INPUT|LVCMOS25*|2||||NONE||LOCATED|NO|NONE| +M7|||GND|||||||||||| +M8|||VCCO_2|||2|||||2.50|||| +M9||DIFFS|IO_L08N_2/A22|UNUSED||2||||||||| +M10||DIFFS|IO_L09N_2/A20|UNUSED||2||||||||| +M11|LED<1>|IOB|IO_L10N_2/VS1/A18|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +M12||DIFFM|IO_L02P_1/A14|UNUSED||1||||||||| +M13||DIFFS|IO_L02N_1/A13|UNUSED||1||||||||| +M14|||VCCO_1|||1|||||3.30|||| +N1||DIFFS|IO_L01N_2/INIT_B|UNUSED||2||||||||| +N2||DIFFS|IO_L02N_2/MOSI/CSI_B|UNUSED||2||||||||| +N3||DIFFSI|IP/VREF_2|UNUSED||2||||||||| +N4|LED<5>|IOB|IO_L03N_2/D6/GCLK13|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +N5|LED<4>|IOB|IO_L04N_2/D3/GCLK15|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +N6||DIFFSI|IP_L05N_2/M2/GCLK1|UNUSED||2||||||||| +N7||IOB|IO/M1|UNUSED||2||||||||| +N8||DIFFS|IO_L07N_2/DIN/D0|UNUSED||2||||||||| +N9||DIFFM|IO_L08P_2/A23|UNUSED||2||||||||| +N10||DIFFM|IO_L09P_2/A21|UNUSED||2||||||||| +N11||DIFFM|IO_L10P_2/VS2/A19|UNUSED||2||||||||| +N12||DIFFS|IO_L11N_2/CCLK|UNUSED||2||||||||| +N13||DIFFM|IO_L01P_1/A16|UNUSED||1||||||||| +N14||DIFFS|IO_L01N_1/A15|UNUSED||1||||||||| +P1||DIFFM|IO_L02P_2/DOUT/BUSY|UNUSED||2||||||||| +P2|||VCCINT||||||||1.2|||| +P3|||VCCO_2|||2|||||2.50|||| +P4|LED<6>|IOB|IO/D5|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +P5|||GND|||||||||||| +P6|LED<3>|IOB|IO_L06P_2/D2/GCLK2|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +P7|LED<2>|IOB|IO_L06N_2/D1/GCLK3|OUTPUT|LVCMOS25*|2|12|SLOW|NONE**|||LOCATED|NO|NONE| +P8||DIFFM|IO_L07P_2/M0|UNUSED||2||||||||| +P9|||VCCAUX||||||||2.5|||| +P10|||GND|||||||||||| +P11||IOB|IO/VREF_2|UNUSED||2||||||||| +P12||DIFFM|IO_L11P_2/VS0/A17|UNUSED||2||||||||| +P13|||DONE|||||||||||| +P14|||GND|||||||||||| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/main.par b/main.par new file mode 100644 index 0000000..6304572 --- /dev/null +++ b/main.par @@ -0,0 +1,209 @@ +Release 14.1 par P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +ALECO-PC:: Thu Feb 21 20:21:13 2013 + +par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf + + +Constraints file: main.pcf. +Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx\14.1\ISE_DS\ISE\. + "main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5 + +Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts) + +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all + internal clocks in this design. Because there are not defined timing requirements, a timing score will not be + reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. + Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + +Device speed data version: "PRODUCTION 1.27 2012-04-23". + + +Design Summary Report: + + Number of External IOBs 19 out of 92 20% + + Number of External Input IOBs 1 + + Number of External Input IBUFs 1 + Number of LOCed External Input IBUFs 1 out of 1 100% + + + Number of External Output IOBs 18 + + Number of External Output IOBs 18 + Number of LOCed External Output IOBs 18 out of 18 100% + + + Number of External Bidir IOBs 0 + + + Number of BUFGMUXs 1 out of 24 4% + Number of Slices 52 out of 2448 2% + Number of SLICEMs 0 out of 1224 0% + + + +Overall effort level (-ol): High +Placer effort level (-pl): High +Placer cost table entry (-t): 1 +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 1 secs +Finished initial Timing Analysis. REAL time: 1 secs + + +Starting Placer +Total REAL time at the beginning of Placer: 1 secs +Total CPU time at the beginning of Placer: 1 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:130c5420) REAL time: 1 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:130c5420) REAL time: 1 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:130c5420) REAL time: 1 secs + +Phase 4.2 Initial Clock and IO Placement + +Phase 4.2 Initial Clock and IO Placement (Checksum:2104b6b4) REAL time: 1 secs + +Phase 5.30 Global Clock Region Assignment +Phase 5.30 Global Clock Region Assignment (Checksum:2104b6b4) REAL time: 1 secs + +Phase 6.36 Local Placement Optimization +Phase 6.36 Local Placement Optimization (Checksum:2104b6b4) REAL time: 1 secs + +Phase 7.8 Global Placement +......... +.. +Phase 7.8 Global Placement (Checksum:5dd09b6d) REAL time: 4 secs + +Phase 8.5 Local Placement Optimization +Phase 8.5 Local Placement Optimization (Checksum:5dd09b6d) REAL time: 4 secs + +Phase 9.18 Placement Optimization +Phase 9.18 Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs + +Phase 10.5 Local Placement Optimization +Phase 10.5 Local Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs + +Total REAL time to Placer completion: 4 secs +Total CPU time to Placer completion: 4 secs +Writing design to file main.ncd + + + +Starting Router + + +Phase 1 : 319 unrouted; REAL time: 7 secs + +Phase 2 : 284 unrouted; REAL time: 7 secs + +Phase 3 : 35 unrouted; REAL time: 7 secs + +Phase 4 : 69 unrouted; (Par is working to improve performance) REAL time: 7 secs + +Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs + +Updating file: main.ncd with current fully routed design. + +Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs + +Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs + +Updating file: main.ncd with current fully routed design. + +Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs + +Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs + +Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs + +Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs + +Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs +WARNING:Route:455 - CLK Net:VGADriver/W may have excessive skew because + 2 CLK pins and 0 NON_CLK pins failed to route using a CLK template. + +Total REAL time to Router completion: 10 secs +Total CPU time to Router completion: 9 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +************************** +Generating Clock Report +************************** + ++---------------------+--------------+------+------+------------+-------------+ +| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| ++---------------------+--------------+------+------+------------+-------------+ +| CLK_BUFGP | BUFGMUX_X2Y1| No | 25 | 0.037 | 0.098 | ++---------------------+--------------+------+------+------------+-------------+ +| VGADriver/W | Local| | 2 | 0.000 | 1.219 | ++---------------------+--------------+------+------+------------+-------------+ + +* Net Skew is the difference between the minimum and maximum routing +only delays for the net. Note this is different from Clock Skew which +is reported in TRCE timing report. Clock Skew is the difference between +the minimum and maximum path delays which includes logic delays. + +* The fanout is the number of component pins not the individual BEL loads, +for example SLICE loads not FF loads. + +Timing Score: 0 (Setup: 0, Hold: 0) + +Asterisk (*) preceding a constraint indicates it was not met. + This may be due to a setup or hold violation. + +---------------------------------------------------------------------------------------------------------- + Constraint | Check | Worst Case | Best Case | Timing | Timing + | | Slack | Achievable | Errors | Score +---------------------------------------------------------------------------------------------------------- + Autotimespec constraint for clock net CLK | SETUP | N/A| 5.493ns| N/A| 0 + _BUFGP | HOLD | 1.410ns| | 0| 0 +---------------------------------------------------------------------------------------------------------- + + +All constraints were met. +INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the + constraint is not analyzed due to the following: No paths covered by this + constraint; Other constraints intersect with this constraint; or This + constraint was disabled by a Path Tracing Control. Please run the Timespec + Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 10 secs +Total CPU time to PAR completion: 9 secs + +Peak Memory Usage: 228 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 1 +Number of info messages: 1 + +Writing design to file main.ncd + + + +PAR done! diff --git a/main.pcf b/main.pcf new file mode 100644 index 0000000..52f804c --- /dev/null +++ b/main.pcf @@ -0,0 +1,27 @@ +//! ************************************************************************** +// Written by: Map P.15xf on Thu Feb 21 20:21:10 2013 +//! ************************************************************************** + +SCHEMATIC START; +COMP "HS" LOCATE = SITE "J14" LEVEL 1; +COMP "LED<0>" LOCATE = SITE "M5" LEVEL 1; +COMP "LED<1>" LOCATE = SITE "M11" LEVEL 1; +COMP "LED<2>" LOCATE = SITE "P7" LEVEL 1; +COMP "RGB<0>" LOCATE = SITE "H13" LEVEL 1; +COMP "LED<3>" LOCATE = SITE "P6" LEVEL 1; +COMP "RGB<1>" LOCATE = SITE "J13" LEVEL 1; +COMP "LED<4>" LOCATE = SITE "N5" LEVEL 1; +COMP "RGB<2>" LOCATE = SITE "F14" LEVEL 1; +COMP "LED<5>" LOCATE = SITE "N4" LEVEL 1; +COMP "RGB<3>" LOCATE = SITE "G13" LEVEL 1; +COMP "LED<6>" LOCATE = SITE "P4" LEVEL 1; +COMP "RGB<4>" LOCATE = SITE "G14" LEVEL 1; +COMP "LED<7>" LOCATE = SITE "G1" LEVEL 1; +COMP "RGB<5>" LOCATE = SITE "C14" LEVEL 1; +COMP "RGB<6>" LOCATE = SITE "D13" LEVEL 1; +COMP "VS" LOCATE = SITE "K13" LEVEL 1; +COMP "RGB<7>" LOCATE = SITE "F13" LEVEL 1; +COMP "CLK" LOCATE = SITE "M6" LEVEL 1; +NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT; +SCHEMATIC END; + diff --git a/main.prj b/main.prj new file mode 100644 index 0000000..f697910 --- /dev/null +++ b/main.prj @@ -0,0 +1,2 @@ +vhdl work "vga.vhd" +vhdl work "main.vhd" diff --git a/main.ptwx b/main.ptwx new file mode 100644 index 0000000..f84f420 --- /dev/null +++ b/main.ptwx @@ -0,0 +1,332 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Autotimespec constraint for clock net CLK_BUFGP0INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI. diff --git a/main.stx b/main.stx new file mode 100644 index 0000000..e69de29 diff --git a/main.syr b/main.syr new file mode 100644 index 0000000..8a23c53 --- /dev/null +++ b/main.syr @@ -0,0 +1,423 @@ +Release 14.1 - xst P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Reading design: main.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "main.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "main" +Output Format : NGC +Target Device : xc3s250e-5-cp132 + +---- Source Options +Top Module Name : main +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 24 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. +Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work. +Architecture behavioral of Entity main is up to date. + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for entity
in library (architecture ). + +Analyzing hierarchy for entity in library (architecture ). + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity
in library (Architecture ). +WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: + , , +Entity
analyzed. Unit
generated. + +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "C:/fpga/pong/vga.vhd". +WARNING:Xst:1305 - Output is never assigned. Tied to value 00000000. + Found 1-bit register for signal . + Found 1-bit register for signal . + Found 10-bit register for signal . + Found 10-bit register for signal . + Found 1-bit register for signal . + Found 8-bit register for signal . + Found 10-bit up counter for signal . + Found 11-bit comparator greater for signal created at line 44. + Found 11-bit comparator less for signal created at line 44. + Found 10-bit up counter for signal . + Found 11-bit comparator greater for signal created at line 50. + Found 11-bit comparator less for signal created at line 50. + Found 11-bit comparator greatequal for signal created at line 32. + Found 11-bit comparator greatequal for signal created at line 32. + Found 11-bit comparator less for signal created at line 32. + Found 11-bit comparator less for signal created at line 32. + Found 10-bit adder for signal created at line 37. + Found 10-bit subtractor for signal created at line 37. + Found 10-bit adder for signal created at line 38. + Found 10-bit subtractor for signal created at line 38. + Summary: + inferred 2 Counter(s). + inferred 31 D-type flip-flop(s). + inferred 4 Adder/Subtractor(s). + inferred 8 Comparator(s). +Unit synthesized. + + +Synthesizing Unit
. + Related source file is "C:/fpga/pong/main.vhd". +WARNING:Xst:737 - Found 8-bit latch for signal . Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. + Found 11-bit comparator greatequal for signal created at line 59. + Found 11-bit comparator greatequal for signal created at line 59. + Found 11-bit comparator lessequal for signal created at line 59. + Found 11-bit comparator lessequal for signal created at line 59. + Summary: + inferred 4 Comparator(s). +Unit
synthesized. + + +========================================================================= +HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 4 + 10-bit adder : 2 + 10-bit subtractor : 2 +# Counters : 2 + 10-bit up counter : 2 +# Registers : 6 + 1-bit register : 3 + 10-bit register : 2 + 8-bit register : 1 +# Latches : 1 + 8-bit latch : 1 +# Comparators : 12 + 11-bit comparator greatequal : 4 + 11-bit comparator greater : 2 + 11-bit comparator less : 4 + 11-bit comparator lessequal : 2 + +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Macro Statistics +# Adders/Subtractors : 4 + 10-bit adder : 2 + 10-bit subtractor : 2 +# Counters : 2 + 10-bit up counter : 2 +# Registers : 31 + Flip-Flops : 31 +# Latches : 1 + 8-bit latch : 1 +# Comparators : 12 + 11-bit comparator greatequal : 4 + 11-bit comparator greater : 2 + 11-bit comparator less : 4 + 11-bit comparator lessequal : 2 + +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= +INFO:Xst:2261 - The FF/Latch <7> in Unit is equivalent to the following 4 FFs/Latches, which will be removed : <6> <5> <1> <0> +INFO:Xst:2261 - The FF/Latch <4> in Unit is equivalent to the following 2 FFs/Latches, which will be removed : <3> <2> + +Optimizing unit
... + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +INFO:Xst:2261 - The FF/Latch in Unit
is equivalent to the following 2 FFs/Latches, which will be removed : +INFO:Xst:2261 - The FF/Latch in Unit
is equivalent to the following 4 FFs/Latches, which will be removed : +Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 2. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Macro Statistics +# Registers : 45 + Flip-Flops : 45 + +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : main.ngr +Top Level Output File Name : main +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : No + +Design Statistics +# IOs : 19 + +Cell Usage : +# BELS : 189 +# GND : 1 +# INV : 11 +# LUT1 : 33 +# LUT2 : 1 +# LUT2_L : 1 +# LUT3 : 6 +# LUT3_L : 3 +# LUT4 : 29 +# LUT4_D : 1 +# LUT4_L : 4 +# MUXCY : 45 +# MUXF5 : 3 +# VCC : 1 +# XORCY : 50 +# FlipFlops/Latches : 47 +# FD : 1 +# FDE : 20 +# FDR : 13 +# FDRE : 10 +# FDS : 1 +# LD : 2 +# Clock Buffers : 1 +# BUFGP : 1 +# IO Buffers : 18 +# OBUF : 18 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 3s250ecp132-5 + + Number of Slices: 50 out of 2448 2% + Number of Slice Flip Flops: 47 out of 4896 0% + Number of 4 input LUTs: 89 out of 4896 1% + Number of IOs: 19 + Number of bonded IOBs: 19 out of 92 20% + Number of GCLKs: 1 out of 24 4% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +-----------------------------------+------------------------+-------+ +Clock Signal | Clock buffer(FF name) | Load | +-----------------------------------+------------------------+-------+ +VGADriver/W | NONE(inrgb_4) | 2 | +CLK | BUFGP | 45 | +-----------------------------------+------------------------+-------+ +INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: 5.905ns (Maximum Frequency: 169.349MHz) + Minimum input arrival time before clock: No path found + Maximum output required time after clock: 4.221ns + Maximum combinational path delay: No path found + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default period analysis for Clock 'CLK' + Clock period: 5.905ns (frequency: 169.349MHz) + Total number of paths / destination ports: 1505 / 95 +------------------------------------------------------------------------- +Delay: 5.905ns (Levels of Logic = 4) + Source: VGADriver/vert_6 (FF) + Destination: VGADriver/Y_9 (FF) + Source Clock: CLK rising + Destination Clock: CLK rising + + Data Path: VGADriver/vert_6 to VGADriver/Y_9 + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDRE:C->Q 4 0.514 0.651 VGADriver/vert_6 (VGADriver/vert_6) + LUT2_L:I0->LO 1 0.612 0.103 VGADriver/vert_cmp_eq00001_SW0 (VGADriver/X_and000093) + LUT4:I3->O 3 0.612 0.454 VGADriver/vert_cmp_eq00001 (VGADriver/N7) + LUT4_D:I3->O 4 0.612 0.502 VGADriver/X_and0000136 (VGADriver/X_and0000136) + LUT4:I3->O 10 0.612 0.750 VGADriver/X_and0000151_2 (VGADriver/X_and0000151_1) + FDE:CE 0.483 VGADriver/Y_0 + ---------------------------------------- + Total 5.905ns (3.445ns logic, 2.460ns route) + (58.3% logic, 41.7% route) + +========================================================================= +Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK' + Total number of paths / destination ports: 10 / 10 +------------------------------------------------------------------------- +Offset: 4.221ns (Levels of Logic = 1) + Source: VGADriver/RGB_7 (FF) + Destination: RGB<7> (PAD) + Source Clock: CLK rising + + Data Path: VGADriver/RGB_7 to RGB<7> + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + FDS:C->Q 5 0.514 0.538 VGADriver/RGB_7 (VGADriver/RGB_7) + OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>) + ---------------------------------------- + Total 4.221ns (3.683ns logic, 0.538ns route) + (87.3% logic, 12.7% route) + +========================================================================= + + +Total REAL time to Xst completion: 6.00 secs +Total CPU time to Xst completion: 5.42 secs + +--> + +Total memory usage is 217424 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 3 ( 0 filtered) +Number of infos : 5 ( 0 filtered) + diff --git a/main.twr b/main.twr new file mode 100644 index 0000000..a6f0af3 --- /dev/null +++ b/main.twr @@ -0,0 +1,78 @@ +-------------------------------------------------------------------------------- +Release 14.1 Trace (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n +3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf + +Design file: main.ncd +Physical constraint file: main.pcf +Device,package,speed: xc3s250e,cp132,-5 (PRODUCTION 1.27 2012-04-23) +Report level: verbose report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. +INFO:Timing:3390 - This architecture does not support a default System Jitter + value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock + Uncertainty calculation. +INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and + 'Phase Error' calculations, these terms will be zero in the Clock + Uncertainty calculation. Please make appropriate modification to + SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase + Error. + + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Clock CLK to Pad +------------+------------+------------------+--------+ + | clk (edge) | | Clock | +Destination | to PAD |Internal Clock(s) | Phase | +------------+------------+------------------+--------+ +HS | 6.320(R)|CLK_BUFGP | 0.000| +RGB<0> | 7.061(R)|CLK_BUFGP | 0.000| +RGB<1> | 7.052(R)|CLK_BUFGP | 0.000| +RGB<2> | 7.348(R)|CLK_BUFGP | 0.000| +RGB<3> | 7.565(R)|CLK_BUFGP | 0.000| +RGB<4> | 7.538(R)|CLK_BUFGP | 0.000| +RGB<5> | 8.606(R)|CLK_BUFGP | 0.000| +RGB<6> | 8.389(R)|CLK_BUFGP | 0.000| +RGB<7> | 7.981(R)|CLK_BUFGP | 0.000| +VS | 6.627(R)|CLK_BUFGP | 0.000| +------------+------------+------------------+--------+ + +Clock to Setup on destination clock CLK +---------------+---------+---------+---------+---------+ + | Src:Rise| Src:Fall| Src:Rise| Src:Fall| +Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| +---------------+---------+---------+---------+---------+ +CLK | 5.493| | | | +---------------+---------+---------+---------+---------+ + + +Analysis completed Thu Feb 21 20:21:26 2013 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 129 MB + + + diff --git a/main.twx b/main.twx new file mode 100644 index 0000000..e496d42 --- /dev/null +++ b/main.twx @@ -0,0 +1,338 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.1 Trace (nt)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n +3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf + +main.ncdmain.ncdmain.pcfmain.pcfxc3s250e-5PRODUCTION 1.27 2012-04-233INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.CLKCLKCLK5.493Thu Feb 21 20:21:26 2013 TraceTrace Settings + +Peak Memory Usage: 129 MB + diff --git a/main.unroutes b/main.unroutes new file mode 100644 index 0000000..df23974 --- /dev/null +++ b/main.unroutes @@ -0,0 +1,9 @@ +Release 14.1 - par P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Thu Feb 21 20:21:23 2013 + +All signals are completely routed. + + + diff --git a/main.ut b/main.ut new file mode 100644 index 0000000..1c9e99e --- /dev/null +++ b/main.ut @@ -0,0 +1,22 @@ +-w +-g DebugBitstream:No +-g Binary:no +-g CRC:Enable +-g ConfigRate:1 +-g ProgPin:PullUp +-g DonePin:PullUp +-g TckPin:PullUp +-g TdiPin:PullUp +-g TdoPin:PullUp +-g TmsPin:PullUp +-g UnusedPin:PullDown +-g UserID:0xFFFFFFFF +-g DCMShutdown:Disable +-g StartUpClk:CClk +-g DONE_cycle:4 +-g GTS_cycle:5 +-g GWE_cycle:6 +-g LCK_cycle:NoWait +-g Security:None +-g DonePipe:Yes +-g DriveDone:No diff --git a/main.vhd b/main.vhd new file mode 100644 index 0000000..a0ea709 --- /dev/null +++ b/main.vhd @@ -0,0 +1,68 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity main is + port ( + CLK : in std_logic; + + LED : out std_logic_vector(7 downto 0); + RGB : out std_logic_vector(7 downto 0); + + HS : out std_logic; + VS : out std_logic + ); +end main; + +architecture Behavioral of main is + component vga is + port ( + CLK : in std_logic; + + LED : out std_logic_vector(7 downto 0); + + IRGB : in std_logic_vector(7 downto 0); + + RGB : out std_logic_vector(7 downto 0); + + W : out std_logic; + X : out std_logic_vector(9 downto 0); + Y : out std_logic_vector(9 downto 0); + + VS : out std_logic; + HS : out std_logic + ); + end component; + + signal inrgb : std_logic_vector(7 downto 0) := "00000000"; + + signal w : std_logic; + signal x : std_logic_vector(9 downto 0); + signal y : std_logic_vector(9 downto 0); +begin + + VGADriver : component vga port map ( + CLK => CLK, + LED => LED, + HS => HS, + VS => VS, + RGB => RGB, + IRGB => inrgb, + W => w, + X => x, + Y => y + ); + + process (CLK) begin + if w = '1' then + if x >= 300 and x <= 340 and y >= 220 and y <= 260 then + inrgb <= "11100011"; + else + inrgb <= "00011100"; + end if; + end if; + end process; + +end Behavioral; + diff --git a/main.xpi b/main.xpi new file mode 100644 index 0000000..d043f7f --- /dev/null +++ b/main.xpi @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF diff --git a/main.xst b/main.xst new file mode 100644 index 0000000..cfca244 --- /dev/null +++ b/main.xst @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn main.prj +-ifmt mixed +-ofn main +-ofmt NGC +-p xc3s250e-5-cp132 +-top main +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 100000 +-bufg 24 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/main_bitgen.xwbt b/main_bitgen.xwbt new file mode 100644 index 0000000..568bb3c --- /dev/null +++ b/main_bitgen.xwbt @@ -0,0 +1,8 @@ +INTSTYLE=ise +INFILE=C:\fpga\pong\main.ncd +OUTFILE=C:\fpga\pong\main.bit +FAMILY=Spartan3E +PART=xc3s250e-5cp132 +WORKINGDIR=C:\fpga\pong +LICENSE=WebPack +USER_INFO=__0_0_0 diff --git a/main_envsettings.html b/main_envsettings.html new file mode 100644 index 0000000..ff5340f --- /dev/null +++ b/main_envsettings.html @@ -0,0 +1,509 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
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C:\Program Files\IVI Foundation\VISA\Win64\Bin\;
C:\Program Files (x86)\IVI Foundation\VISA\WinNT\Bin;
L:\fortran\g95\bin
XILINXC:\Xilinx\14.1\ISE_DS\ISE\C:\Xilinx\14.1\ISE_DS\ISE\C:\Xilinx\14.1\ISE_DS\ISE\C:\Xilinx\14.1\ISE_DS\ISE\
XILINX_DSPC:\Xilinx\14.1\ISE_DS\ISEC:\Xilinx\14.1\ISE_DS\ISEC:\Xilinx\14.1\ISE_DS\ISEC:\Xilinx\14.1\ISE_DS\ISE
XILINX_EDKC:\Xilinx\14.1\ISE_DS\EDKC:\Xilinx\14.1\ISE_DS\EDKC:\Xilinx\14.1\ISE_DS\EDKC:\Xilinx\14.1\ISE_DS\EDK
XILINX_PLANAHEADC:\Xilinx\14.1\ISE_DS\PlanAheadC:\Xilinx\14.1\ISE_DS\PlanAheadC:\Xilinx\14.1\ISE_DS\PlanAheadC:\Xilinx\14.1\ISE_DS\PlanAhead
XILINX_VIVADOC:\Xilinx\Vivado\2012.1C:\Xilinx\Vivado\2012.1C:\Xilinx\Vivado\2012.1C:\Xilinx\Vivado\2012.1
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn main.prj 
-ifmt mixedMIXED
-ofn main 
-ofmt NGCNGC
-p xc3s250e-5-cp132 
-top main 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyNoNO
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsALLCLOCKNETS
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style AutoAUTO
-iobuf YESYES
-max_fanout 100000500
-bufg 2424
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Translation Property Settings
Switch NameProperty NameValueDefault Value
-intstyle iseNone
-dd _ngoNone
-p xc3s250e-cp132-5None
-uc pins.ucfNone
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Map Property Settings
Switch NameProperty NameValueDefault Value
-irUse RLOC ConstraintsOFFOFF
-cmOptimization Strategy (Cover Mode)areaarea
-intstyle iseNone
-o main_map.ncdNone
-prPack I/O Registers/Latches into IOBsoffoff
-p xc3s250e-cp132-5None
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Place and Route Property Settings
Switch NameProperty NameValueDefault Value
-t 11
-intstyle ise 
-olPlace & Route Effort Level (Overall)highstd
-w truefalse
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHzIntel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHzIntel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHzIntel(R) Core(TM) i3 CPU 550 @ 3.20GHz/3191 MHz
HostALECO-PCALECO-PCALECO-PCALECO-PC
OS NameMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bitMicrosoft Windows 7 , 64-bit
OS Releasemajor release (build 7600)major release (build 7600)major release (build 7600)major release (build 7600)
+ \ No newline at end of file diff --git a/main_guide.ncd b/main_guide.ncd new file mode 100644 index 0000000..bda6523 --- /dev/null +++ b/main_guide.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4424:XlxV32DM 3fff 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12c0eNqtmm1v3DYSgP+MP+QFOIikRJHS5RBf21wC5Bo0Dvr2IQZFSkVwiJM210MLr/3bb0jOiJSWzkqNU9S74gyHwxHn2SGltn939dsvw2Xr8Iu5chX8Y9XqmtesPWq6/Gjsfy7ZkXLdTquW5khHcsYKTeKo7XI66swrtu4cmsRRW6kz0yvvRLNqaBom1y0415WmXHdt2bpry9Zhev/7H35qfxf/mGeRNcEkPo11/968u7Lh7+V78/FvV7+8F/2HaRL9R/Ob7j/B3/+aKzGq/g8rPvGmGvnUH75+/eL7b87fvHn9z1c/dox3L17Rxcvvv/r3qwvedBcvv/kB/rz64XDg46qHOuogROzw7PzizeFQt/3h2bMfL198++LNpVfs/Leq820Xr2PLxWuw3b08f/PV88tXry+fPQNpd/HTt19F8bn/CpbkF1tCQ8GlnwqGfvpLLn2Rpc+5xFaGnr/41/NTlljTH45vIdw43h8OXz958ODB7Tl75P/yR+fi4eNz/hD+sIePzuuHB84WSl6lBvEDuAhfoMOBuaWOeBxFYAJsgtzmcmiJ3cVDHKJdiOsoRn/q6M/DR2GgKde89c4+CF+8x7feFqRN1CBnhXfEC9pZ8BTUH4EFEWZwECRJUYApPLrFefJ5Qjjt+fLAZd6TRqOhH+AAXnFcKj6ebUTtMOYtDep90ssOT2+T6ZX2ykUYTOR9vfJt7pe/Y17LLLWSNfQ+d2e+wbcYbQrEIwxEU5QfTWu+f6BHKuJxlOJSUSuN4PvTIEInQgzyxRF1lvLbEOS4WEkukzy/PQfGFwLUblPj7VJdHUtu7xDdpl66IKJus2fLm3lgLBc8jo7x1HZLjXZu85GaA/E0xhRv9W1x7CR8fCwUS2EcLHpbHWKEztkhzhqUDl7/cPP06cdBDf3Tp38ILrpnXdux6ws1dZZ11nZMCK7N2DWyGa+vRMU61sMH72R/xqep45Prby6UK6j3F4PtBJddlTVL1nvto+am3KzKzabcPPTOzwHa7pxDf8YktEjXn0kFFtr+api6hnHpJKv7s2EMjWe2gp792djAZd3/74113qj/T/C7Tbeia9r+uxE8uL75zo3+48wNXaP6M1V5GehUcQQmJ/ii/BcYswqiEN1Rkj+y/3Pknf/B/3Nk4fPl4Dp5fSYq0IEbAOP2ZwJ6w0UN1jjMCj7gSoWPm+du6n9mbd3xa111MHNoafuXFoaOVkx/1kJ/1V9pGPtmwPiJrladUte/uqb/1bH+uZP9z1KDmcZ0je5u3qkW9J6zlve/O9fxqu8/GH7UxKfmqI0JC21nYw3DDDBdGLBfa5iVBjvS0CsNfqShVhriSKNdadRHGnKl0RxpNCsNeaRRrzTalcYgUGHgxWgMbClfx2KolvJ1JMy0lK/jAMt3IV9HwbilfB0DY5fydQTMsJSv5j9w7hNWdaabriEZhk5DHjpY97A/kX4h9O8Ujx/+hvUf1BiudLh9DpKwnnq4tHQJSeFXXtD6ICof/34YVeACxOraG4f9Sh8Ga6HEboLKzcCU/1JnSrq/cqbzWeogcD7bQp+mf9eI4ETs+sEO4YrVkiw1K0smWpIrS/K0JT8PnlkagiUr0FKDlmCrJqs5BBCRD7qJJjg3S2caFkwoHU3wAU3oFOk6hjhYgDUsyNKwssSjJQwQd2jJnLSkq+W0GliWYxusTfHfiBOs0eaQT1DybIKjWd7bRmMXB/dWUBx9GohMCe9Iu7oj49Ed0WghuJxbiHeC0x2Y7uj5idc+bOL6ib8TivdPfBzh8y38f/NJqUxYo7AGYQvC0ffk10/8goIQPYGpwgeYDFjhsZdu+id+flZ7SXQzdoFlBAahJajAZ+ysLFkdO1n1b7UfiilHHevY0YvJNo7a0KjDbDKOGpfpdRgsmLS+lbOkD/e+fwvpGNqr5H1oh3QNLtTJBTv0cdo1ul4HjSYFBDTeKt9v1LERkjxoQ+/gr6mSuSiY/OdbKCBu/GrmZfCMafWKz4NnPA0epmQZKvV+qLRlqPC9UOG6PoLKiexb4mVc4MWW8dLux4sr40Xux4u6R7y4FV4UdrEJLxPfgCDNyggS2xHEywhipxA0jpQ2MnLEYUZrSXmrsrzVihKnJYYoTHiOHUOhGFLYLVObU7vNU5traoe1NzMnLkQR/cKBahyIxYHiqufRlznjY1Zhx0iKFknBIykSVi1i1SWsRoxg99iNBTIoseS1RV67xGsu2jRzikmA4CSSpz7IE8VKyBQTmpzv4Zc8sLbTwCBWLSE0bYaQIwjBhws6xwxSZQZV+xmkiwxi4+7CxqlyYWM/W9i4BXnGMnma/eSZyuSp95KHOb1KUREsaSyRoFZd8gY+WDBBs2JMnOYNY80W4IgicNi0HTh1ETjMnQJOTNuQYfijDM7MGZaSc8TknFJyZuk3YvpNWfrpCbMMIp0Ra8haGbQ67wSrKSNVyEgfW6SKSu5Ffmh0s6ZKQ1NfnbjDxZj6xSLJERkFIdWQKyojHZ8LtnHBRT6XVNOCo2KigTQNpHEgrG4Yk8nDOLuGgKPSYORcrNOETsORNUIRILhzHkX1AkV1ta8eUst9mZ4v7VG1FIEVL2t/Oc6Xrb+c5sumWFqZItaY3Y+1oYw1sx9ra59ixmisYYS7q6CKHJi3b+8kny9tDj1RlaEndkNPsDL0+H7o+Sg0R9AbcIcphruKrGzSkCr5pKXwl2K+ZH2OSL0FkcMWRDZlRA7bESnLiNSnt4WMUnygFKdtlcRENlT8gCTBzlRZK8GOc6oyRLUkDNUrgi0IY6hcAW+zisxkrd62WkIXWgHFWgdEGpqAQYgOCFFJEJ33r0MG0bpK/XDiuIvVDfFZJ5Vosin8fMBMw88HzKzw8+GlHKXzz4dpstj5mcTq1GWtECI9BcBSLJRBwGpCr03zipKB0GvSXaApIXqHdB/oLhN64cekg1qzY3yJXlZGb5G5C9ZOd7B2wdiaGFtiqy2zdf9ZmLNlIiKla/55Ii5IuDjXErxMQrafhKJMwmo/CcciCTVuhoX9PAkXBKyIgDn5NmxGWVgdBajtOOtSZajJk1ATllY5x1Xe0vp3JBEoUSgxc/aNKSfZNGWtKSfnnazFzKOtbC2SPtlHiqrMUqJobn8uGSeyD7dgJp1P0HlWC7bqNKecrTUnfFkinJ3DsUa7zfBrhqyV8Jt4x5F3It/L2hSRQGGtIn0zEnIkoUgkjGxGHyNi2xmxkBPNUDwd42zDsfzp43i94The6zKCmt0I0qZc3ond5V380TzetfI7dq0ZrmRTxFU77caVlEVctePuc7J2uMdzMruh3jJ1GU31ZjSZpowmfrrespgOcCdCOkAcj4/hvbBG4dExvI6FwGgxiSUyxPcK6W1qZFpL2aWxxvEtUYV2aS3tMGFRpWN4Q+jQtPEzYraNHen4HHwkkzgqVR9tXi82NunnlGqG5H1+DK91ciESBYsw02BdN1eJ2hSO4WkrrVfH8BoFps6P4RtXBg3fvO1cFTvFvaIeyjBh+2FiizCZdp/Ct+7LTuEXxZBsy3Rx++miynSx++kyfRld8j3fOG04ha+3EEiWCVRtJ1BbJNC4+RBex03DSI/VWnp4BgFLWdvSCZC2RBA8szFUQzTUEe7ZIrGp1IJVkZcrLYEAll6qOVp68KcHGghPtg3uQ+Oa59GXdAivh9QxcgIrCdOuDuHBjwhVlRUu2qTusZvMD+Ft1pdj33kb1/I0c4rJ8hBex/pwmqHJUkxocrj9aqYygcQGAp1+AKhdkTxuP3jGIniG3eBR7K+CJweOLgNn2A8cUwaO2Q0cJe6vnJmqDcDZcgpvVBE4djtvdJE3ZjtvXEyF+fk/JY8SGW9C8EI6jogBRYWHpnJnLjzMkjdzGaQXvFGkDysu8UbRuRf4hQPhiYhRxJvZ9THnjUsdI29GBIde80Yjb0zOG5u6x26qyBuNvDE5b+o0c4rJijdjDPJc3YkUE5oc8kayMm/q+614piJ39G7umKrInXY/d5r7LHiGMn/2v9UkbZk/+99qis+q76fgmdgG/sgt/DFF/qjt/BmK/JHb+TPF1GDEHzqphnhl/KEnhrDeEAv0S02Hq3L+1bcL/sj5t31Y8oeyFlZexh96+A9+4UC0e8PXq9h8wg5fMv5MqWPgj6kQJMOaPwPyx+b8GVP32M0U+TMgf2zOH5lmTjFZ8sdUMcj06KBtUkxocsQfAYsGqqrOLfnTbDxtPgEew4rg2X1sw+Mj2Ht6TUm6Mi/2v6YkxzIv9r+mpO4+fhGbQcHYhq0RC6/pHlNgx7mLK1JAnHwTwDBaoQyzxuH55PyQBySYiPRbSQcsKSscZsWYHWHyKpmOh8Hzlooeekk3W8QjEjrKlXhMDO7gO4wkUTqjhRTJUs4WWSc7GYvYfNphGGa5LTy5kg4BMWZPruhpmf9CriExTZIQMWH9DPaOt4f4X313GhL6HZN1+ZkQZxtOba0oZr8Ydtcdti7WHULvPrW1rnxqW29/idq51YMdxAe9a2S34YOC6y2uHxUhRuido3EbRjKLlt1f+cG42FBb2LFIFWE2Y8VOZayok8e5Ax1yuGViWtp0uGViWir/YYXGg1WLbLAjptlAxxw2Ox+J6zC01qkYmDPZYSa7LJNjEuBYgXkW30C2E7JvnLL+HPsT2GaGWIHdxvnEFKiHVZDPxyilV4+qNk09zozeCq+aFCyac5SMbXIEllL0xH956//44bLpB8hyGm6gbZ9lWR1naXtn8T1y30LeNPHhkr8FRXCJ/e9efwZYtimzqN3PIllmUbN7E2Sbeyxq3FSmkriTSv8HLV2ysQ==###4160:XlxV32DM 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\ No newline at end of file diff --git a/main_map.map b/main_map.map new file mode 100644 index 0000000..12a71c0 --- /dev/null +++ b/main_map.map @@ -0,0 +1,71 @@ +Release 14.1 Map P.15xf (nt) +Xilinx Map Application Log File for Design 'main' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off +-c 100 -o main_map.ncd main.ngd main.pcf +Target Device : xc3s250e +Target Package : cp132 +Target Speed : -5 +Mapper Version : spartan3e -- $Revision: 1.55 $ +Mapped Date : Thu Feb 21 20:21:08 2013 + +Mapping design into LUTs... +Running directed packing... +Running delay-based LUT packing... +Running related packing... +Updating timing models... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 0 +Logic Utilization: + Total Number Slice Registers: 47 out of 4,896 1% + Number used as Flip Flops: 45 + Number used as Latches: 2 + Number of 4 input LUTs: 58 out of 4,896 1% +Logic Distribution: + Number of occupied Slices: 52 out of 2,448 2% + Number of Slices containing only related logic: 52 out of 52 100% + Number of Slices containing unrelated logic: 0 out of 52 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 92 out of 4,896 1% + Number used as logic: 58 + Number used as a route-thru: 34 + + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + + Number of bonded IOBs: 19 out of 92 20% + Number of BUFGMUXs: 1 out of 24 4% + +Average Fanout of Non-Clock Nets: 2.67 + +Peak Memory Usage: 209 MB +Total REAL time to MAP completion: 1 secs +Total CPU time to MAP completion: 1 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Mapping completed. +See MAP report file "main_map.mrp" for details. diff --git a/main_map.mrp b/main_map.mrp new file mode 100644 index 0000000..9b7b158 --- /dev/null +++ b/main_map.mrp @@ -0,0 +1,169 @@ +Release 14.1 Map P.15xf (nt) +Xilinx Mapping Report File for Design 'main' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off +-c 100 -o main_map.ncd main.ngd main.pcf +Target Device : xc3s250e +Target Package : cp132 +Target Speed : -5 +Mapper Version : spartan3e -- $Revision: 1.55 $ +Mapped Date : Thu Feb 21 20:21:08 2013 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 0 +Logic Utilization: + Total Number Slice Registers: 47 out of 4,896 1% + Number used as Flip Flops: 45 + Number used as Latches: 2 + Number of 4 input LUTs: 58 out of 4,896 1% +Logic Distribution: + Number of occupied Slices: 52 out of 2,448 2% + Number of Slices containing only related logic: 52 out of 52 100% + Number of Slices containing unrelated logic: 0 out of 52 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 92 out of 4,896 1% + Number used as logic: 58 + Number used as a route-thru: 34 + + The Slice Logic Distribution report is not meaningful if the design is + over-mapped for a non-slice resource or if Placement fails. + + Number of bonded IOBs: 19 out of 92 20% + Number of BUFGMUXs: 1 out of 24 4% + +Average Fanout of Non-Clock Nets: 2.67 + +Peak Memory Usage: 209 MB +Total REAL time to MAP completion: 1 secs +Total CPU time to MAP completion: 1 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- + +Section 3 - Informational +------------------------- +INFO:MapLib:562 - No environment variables are currently set. + +Section 4 - Removed Logic Summary +--------------------------------- + 2 block(s) optimized away + +Section 5 - Removed Logic +------------------------- + +Optimized Block(s): +TYPE BLOCK +GND XST_GND +VCC XST_VCC + +To enable printing of redundant blocks removed and signals merged, set the +detailed map report option and rerun map. + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| CLK | IBUF | INPUT | LVCMOS25 | | | | | | 0 / 0 | +| HS | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| LED<0> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<1> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<2> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<3> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<4> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| LED<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | +| RGB<0> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<1> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<2> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<3> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<4> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<5> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<6> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| RGB<7> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | +| VS | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +This design was not run using timing mode. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +No control set information for this architecture. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/main_map.ncd b/main_map.ncd new file mode 100644 index 0000000..384e5e8 --- /dev/null +++ b/main_map.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###4436:XlxV32DM 3fdc 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+ + + + diff --git a/main_pad.csv b/main_pad.csv new file mode 100644 index 0000000..0b8315e --- /dev/null +++ b/main_pad.csv @@ -0,0 +1,163 @@ +#Release 14.1 - par P.15xf (nt) +#Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +#Thu Feb 21 20:21:23 2013 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: main_map.ncd +#OUTPUT FILE: main_pad.csv +#PART TYPE: xc3s250e +#SPEED GRADE: -5 +#PACKAGE: cp132 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, +A1,,,PROG_B,,,,,,,,,,,, +A2,,,TDI,,,,,,,,,,,, +A3,,DIFFM,IO_L11P_0,UNUSED,,0,,,,,,,,, +A4,,,GND,,,,,,,,,,,, +A5,,,VCCAUX,,,,,,,,2.5,,,, +A6,,,VCCO_0,,,0,,,,,any******,,,, +A7,,DIFFM,IO_L07P_0/GCLK10,UNUSED,,0,,,,,,,,, +A8,,,GND,,,,,,,,,,,, +A9,,DIFFS,IO_L05N_0/GCLK7,UNUSED,,0,,,,,,,,, +A10,,DIFFM,IO_L04P_0/GCLK4,UNUSED,,0,,,,,,,,, +A11,,,VCCINT,,,,,,,,1.2,,,, +A12,,DIFFS,IO_L02N_0,UNUSED,,0,,,,,,,,, +A13,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,, +A14,,,TDO,,,,,,,,,,,, +B1,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,, +B2,,DIFFM,IO_L01P_3,UNUSED,,3,,,,,,,,, +B3,,DIFFS,IO_L11N_0/HSWAP,UNUSED,,0,,,,,,,,, +B4,,DIFFM,IO_L10P_0,UNUSED,,0,,,,,,,,, +B5,,DIFFM,IO_L09P_0,UNUSED,,0,,,,,,,,, +B6,,DIFFM,IO_L08P_0,UNUSED,,0,,,,,,,,, +B7,,DIFFS,IO_L07N_0/GCLK11,UNUSED,,0,,,,,,,,, +B8,,DIFFMI,IP_L06P_0/GCLK8,UNUSED,,0,,,,,,,,, +B9,,DIFFM,IO_L05P_0/GCLK6,UNUSED,,0,,,,,,,,, +B10,,,VCCO_0,,,0,,,,,any******,,,, +B11,,DIFFS,IO_L03N_0/VREF_0,UNUSED,,0,,,,,,,,, +B12,,DIFFM,IO_L02P_0,UNUSED,,0,,,,,,,,, +B13,,,TCK,,,,,,,,,,,, +B14,,,TMS,,,,,,,,,,,, +C1,,,GND,,,,,,,,,,,, +C2,,DIFFS,IO_L02N_3,UNUSED,,3,,,,,,,,, +C3,,DIFFM,IO_L02P_3,UNUSED,,3,,,,,,,,, +C4,,DIFFS,IO_L10N_0,UNUSED,,0,,,,,,,,, +C5,,DIFFS,IO_L09N_0,UNUSED,,0,,,,,,,,, +C6,,DIFFS,IO_L08N_0/VREF_0,UNUSED,,0,,,,,,,,, +C7,,,GND,,,,,,,,,,,, +C8,,DIFFSI,IP_L06N_0/GCLK9,UNUSED,,0,,,,,,,,, +C9,,DIFFS,IO_L04N_0/GCLK5,UNUSED,,0,,,,,,,,, +C10,,,GND,,,,,,,,,,,, +C11,,DIFFM,IO_L03P_0,UNUSED,,0,,,,,,,,, +C12,,DIFFS,IO_L01N_0,UNUSED,,0,,,,,,,,, +C13,,DIFFS,IO_L10N_1/LDC2,UNUSED,,1,,,,,,,,, +C14,RGB<5>,IOB,IO_L10P_1/LDC1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +D1,,DIFFS,IO_L03N_3,UNUSED,,3,,,,,,,,, +D2,,DIFFM,IO_L03P_3,UNUSED,,3,,,,,,,,, +D3,,,VCCINT,,,,,,,,1.2,,,, +D12,,DIFFS,IO_L09N_1/LDC0,UNUSED,,1,,,,,,,,, +D13,RGB<6>,IOB,IO_L09P_1/HDC,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +D14,,,NC,,,,,,,,,,,, +E1,,,VCCO_3,,,3,,,,,2.50,,,, +E2,,IBUF,IP/VREF_3,UNUSED,,3,,,,,,,,, +E3,,,GND,,,,,,,,,,,, +E12,,,VCCAUX,,,,,,,,2.5,,,, +E13,,,VCCO_1,,,1,,,,,3.30,,,, +E14,,,GND,,,,,,,,,,,, +F1,,DIFFM,IO_L05P_3/LHCLK2,UNUSED,,3,,,,,,,,, +F2,,DIFFS,IO_L04N_3/LHCLK1,UNUSED,,3,,,,,,,,, +F3,,DIFFM,IO_L04P_3/LHCLK0,UNUSED,,3,,,,,,,,, +F12,,DIFFS,IO/A0,UNUSED,,1,,,,,,,,, +F13,RGB<7>,IOB,IO_L08N_1/A1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +F14,RGB<2>,IOB,IO_L08P_1/A2,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +G1,LED<7>,IOB,IO_L05N_3/LHCLK3/IRDY2,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE, +G2,,,GND,,,,,,,,,,,, +G3,,DIFFM,IO_L06P_3/LHCLK4/TRDY2,UNUSED,,3,,,,,,,,, +G12,,IBUF,IP/VREF_1,UNUSED,,1,,,,,,,,, +G13,RGB<3>,IOB,IO_L07N_1/A3/RHCLK7,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +G14,RGB<4>,IOB,IO_L07P_1/A4/RHCLK6,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +H1,,DIFFS,IO_L06N_3/LHCLK5,UNUSED,,3,,,,,,,,, +H2,,DIFFM,IO_L07P_3/LHCLK6,UNUSED,,3,,,,,,,,, +H3,,DIFFS,IO_L07N_3/LHCLK7,UNUSED,,3,,,,,,,,, +H12,,DIFFS,IO_L06N_1/A5/RHCLK5,UNUSED,,1,,,,,,,,, +H13,RGB<0>,IOB,IO_L06P_1/A6/RHCLK4/IRDY1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +H14,,,GND,,,,,,,,,,,, +J1,,,GND,,,,,,,,,,,, +J2,,,VCCO_3,,,3,,,,,2.50,,,, +J3,,DIFFS,IO,UNUSED,,3,,,,,,,,, +J12,,DIFFS,IO_L04N_1/A9/RHCLK1,UNUSED,,1,,,,,,,,, +J13,RGB<1>,IOB,IO_L05P_1/A8/RHCLK2,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +J14,HS,IOB,IO_L05N_1/A7/RHCLK3/TRDY1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +K1,,,VCCAUX,,,,,,,,2.5,,,, +K2,,,NC,,,,,,,,,,,, +K3,,IOB,IO/VREF_3,UNUSED,,3,,,,,,,,, +K12,,,GND,,,,,,,,,,,, +K13,VS,IOB,IO/VREF_1,OUTPUT,LVCMOS33,1,8,FAST,NONE**,,,LOCATED,NO,NONE, +K14,,DIFFM,IO_L04P_1/A10/RHCLK0,UNUSED,,1,,,,,,,,, +L1,,DIFFM,IO_L08P_3,UNUSED,,3,,,,,,,,, +L2,,DIFFS,IO_L08N_3,UNUSED,,3,,,,,,,,, +L3,,DIFFM,IO_L09P_3,UNUSED,,3,,,,,,,,, +L12,,,VCCINT,,,,,,,,1.2,,,, +L13,,DIFFM,IO_L03P_1/A12,UNUSED,,1,,,,,,,,, +L14,,DIFFS,IO_L03N_1/A11,UNUSED,,1,,,,,,,,, +M1,,DIFFS,IO_L09N_3,UNUSED,,3,,,,,,,,, +M2,,DIFFM,IO_L01P_2/CSO_B,UNUSED,,2,,,,,,,,, +M3,,,GND,,,,,,,,,,,, +M4,,DIFFM,IO_L03P_2/D7/GCLK12,UNUSED,,2,,,,,,,,, +M5,LED<0>,IOB,IO_L04P_2/D4/GCLK14,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +M6,CLK,IBUF,IP_L05P_2/RDWR_B/GCLK0,INPUT,LVCMOS25*,2,,,,NONE,,LOCATED,NO,NONE, +M7,,,GND,,,,,,,,,,,, +M8,,,VCCO_2,,,2,,,,,2.50,,,, +M9,,DIFFS,IO_L08N_2/A22,UNUSED,,2,,,,,,,,, +M10,,DIFFS,IO_L09N_2/A20,UNUSED,,2,,,,,,,,, +M11,LED<1>,IOB,IO_L10N_2/VS1/A18,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +M12,,DIFFM,IO_L02P_1/A14,UNUSED,,1,,,,,,,,, +M13,,DIFFS,IO_L02N_1/A13,UNUSED,,1,,,,,,,,, +M14,,,VCCO_1,,,1,,,,,3.30,,,, +N1,,DIFFS,IO_L01N_2/INIT_B,UNUSED,,2,,,,,,,,, +N2,,DIFFS,IO_L02N_2/MOSI/CSI_B,UNUSED,,2,,,,,,,,, +N3,,DIFFSI,IP/VREF_2,UNUSED,,2,,,,,,,,, +N4,LED<5>,IOB,IO_L03N_2/D6/GCLK13,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +N5,LED<4>,IOB,IO_L04N_2/D3/GCLK15,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +N6,,DIFFSI,IP_L05N_2/M2/GCLK1,UNUSED,,2,,,,,,,,, +N7,,IOB,IO/M1,UNUSED,,2,,,,,,,,, +N8,,DIFFS,IO_L07N_2/DIN/D0,UNUSED,,2,,,,,,,,, +N9,,DIFFM,IO_L08P_2/A23,UNUSED,,2,,,,,,,,, +N10,,DIFFM,IO_L09P_2/A21,UNUSED,,2,,,,,,,,, +N11,,DIFFM,IO_L10P_2/VS2/A19,UNUSED,,2,,,,,,,,, +N12,,DIFFS,IO_L11N_2/CCLK,UNUSED,,2,,,,,,,,, +N13,,DIFFM,IO_L01P_1/A16,UNUSED,,1,,,,,,,,, +N14,,DIFFS,IO_L01N_1/A15,UNUSED,,1,,,,,,,,, +P1,,DIFFM,IO_L02P_2/DOUT/BUSY,UNUSED,,2,,,,,,,,, +P2,,,VCCINT,,,,,,,,1.2,,,, +P3,,,VCCO_2,,,2,,,,,2.50,,,, +P4,LED<6>,IOB,IO/D5,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +P5,,,GND,,,,,,,,,,,, +P6,LED<3>,IOB,IO_L06P_2/D2/GCLK2,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +P7,LED<2>,IOB,IO_L06N_2/D1/GCLK3,OUTPUT,LVCMOS25*,2,12,SLOW,NONE**,,,LOCATED,NO,NONE, +P8,,DIFFM,IO_L07P_2/M0,UNUSED,,2,,,,,,,,, +P9,,,VCCAUX,,,,,,,,2.5,,,, +P10,,,GND,,,,,,,,,,,, +P11,,IOB,IO/VREF_2,UNUSED,,2,,,,,,,,, +P12,,DIFFM,IO_L11P_2/VS0/A17,UNUSED,,2,,,,,,,,, +P13,,,DONE,,,,,,,,,,,, +P14,,,GND,,,,,,,,,,,, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file diff --git a/main_pad.txt b/main_pad.txt new file mode 100644 index 0000000..bd04cab --- /dev/null +++ b/main_pad.txt @@ -0,0 +1,162 @@ +Release 14.1 - par P.15xf (nt) +Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. + +Thu Feb 21 20:21:23 2013 + + +INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: +1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: main_map.ncd +OUTPUT FILE: main_pad.txt +PART TYPE: xc3s250e +SPEED GRADE: -5 +PACKAGE: cp132 + +Pinout by Pin Number: + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|A1 | | |PROG_B | | | | | | | | | | | | +|A2 | | |TDI | | | | | | | | | | | | +|A3 | |DIFFM |IO_L11P_0 |UNUSED | |0 | | | | | | | | | +|A4 | | |GND | | | | | | | | | | | | +|A5 | | |VCCAUX | | | | | | | |2.5 | | | | +|A6 | | |VCCO_0 | | |0 | | | | |any******| | | | +|A7 | |DIFFM |IO_L07P_0/GCLK10 |UNUSED | |0 | | | | | | | | | +|A8 | | |GND | | | | | | | | | | | | +|A9 | |DIFFS |IO_L05N_0/GCLK7 |UNUSED | |0 | | | | | | | | | +|A10 | |DIFFM |IO_L04P_0/GCLK4 |UNUSED | |0 | | | | | | | | | +|A11 | | |VCCINT | | | | | | | |1.2 | | | | +|A12 | |DIFFS |IO_L02N_0 |UNUSED | |0 | | | | | | | | | +|A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | +|A14 | | |TDO | | | | | | | | | | | | +|B1 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | +|B2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | +|B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | | +|B4 | |DIFFM |IO_L10P_0 |UNUSED | |0 | | | | | | | | | +|B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | | +|B6 | |DIFFM |IO_L08P_0 |UNUSED | |0 | | | | | | | | | +|B7 | |DIFFS |IO_L07N_0/GCLK11 |UNUSED | |0 | | | | | | | | | +|B8 | |DIFFMI |IP_L06P_0/GCLK8 |UNUSED | |0 | | | | | | | | | +|B9 | |DIFFM |IO_L05P_0/GCLK6 |UNUSED | |0 | | | | | | | | | +|B10 | | |VCCO_0 | | |0 | | | | |any******| | | | +|B11 | |DIFFS |IO_L03N_0/VREF_0 |UNUSED | |0 | | | | | | | | | +|B12 | |DIFFM |IO_L02P_0 |UNUSED | |0 | | | | | | | | | +|B13 | | |TCK | | | | | | | | | | | | +|B14 | | |TMS | | | | | | | | | | | | +|C1 | | |GND | | | | | | | | | | | | +|C2 | |DIFFS |IO_L02N_3 |UNUSED | |3 | | | | | | | | | +|C3 | |DIFFM |IO_L02P_3 |UNUSED | |3 | | | | | | | | | +|C4 | |DIFFS |IO_L10N_0 |UNUSED | |0 | | | | | | | | | +|C5 | |DIFFS |IO_L09N_0 |UNUSED | |0 | | | | | | | | | +|C6 | |DIFFS |IO_L08N_0/VREF_0 |UNUSED | |0 | | | | | | | | | +|C7 | | |GND | | | | | | | | | | | | +|C8 | |DIFFSI |IP_L06N_0/GCLK9 |UNUSED | |0 | | | | | | | | | +|C9 | |DIFFS |IO_L04N_0/GCLK5 |UNUSED | |0 | | | | | | | | | +|C10 | | |GND | | | | | | | | | | | | +|C11 | |DIFFM |IO_L03P_0 |UNUSED | |0 | | | | | | | | | +|C12 | |DIFFS |IO_L01N_0 |UNUSED | |0 | | | | | | | | | +|C13 | |DIFFS |IO_L10N_1/LDC2 |UNUSED | |1 | | | | | | | | | +|C14 |RGB<5> |IOB |IO_L10P_1/LDC1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|D1 | |DIFFS |IO_L03N_3 |UNUSED | |3 | | | | | | | | | +|D2 | |DIFFM |IO_L03P_3 |UNUSED | |3 | | | | | | | | | +|D3 | | |VCCINT | | | | | | | |1.2 | | | | +|D12 | |DIFFS |IO_L09N_1/LDC0 |UNUSED | |1 | | | | | | | | | +|D13 |RGB<6> |IOB |IO_L09P_1/HDC |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|D14 | | |NC | | | | | | | | | | | | +|E1 | | |VCCO_3 | | |3 | | | | |2.50 | | | | +|E2 | |IBUF |IP/VREF_3 |UNUSED | |3 | | | | | | | | | +|E3 | | |GND | | | | | | | | | | | | +|E12 | | |VCCAUX | | | | | | | |2.5 | | | | +|E13 | | |VCCO_1 | | |1 | | | | |3.30 | | | | +|E14 | | |GND | | | | | | | | | | | | +|F1 | |DIFFM |IO_L05P_3/LHCLK2 |UNUSED | |3 | | | | | | | | | +|F2 | |DIFFS |IO_L04N_3/LHCLK1 |UNUSED | |3 | | | | | | | | | +|F3 | |DIFFM |IO_L04P_3/LHCLK0 |UNUSED | |3 | | | | | | | | | +|F12 | |DIFFS |IO/A0 |UNUSED | |1 | | | | | | | | | +|F13 |RGB<7> |IOB |IO_L08N_1/A1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|F14 |RGB<2> |IOB |IO_L08P_1/A2 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|G1 |LED<7> |IOB |IO_L05N_3/LHCLK3/IRDY2 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|G2 | | |GND | | | | | | | | | | | | +|G3 | |DIFFM |IO_L06P_3/LHCLK4/TRDY2 |UNUSED | |3 | | | | | | | | | +|G12 | |IBUF |IP/VREF_1 |UNUSED | |1 | | | | | | | | | +|G13 |RGB<3> |IOB |IO_L07N_1/A3/RHCLK7 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|G14 |RGB<4> |IOB |IO_L07P_1/A4/RHCLK6 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|H1 | |DIFFS |IO_L06N_3/LHCLK5 |UNUSED | |3 | | | | | | | | | +|H2 | |DIFFM |IO_L07P_3/LHCLK6 |UNUSED | |3 | | | | | | | | | +|H3 | |DIFFS |IO_L07N_3/LHCLK7 |UNUSED | |3 | | | | | | | | | +|H12 | |DIFFS |IO_L06N_1/A5/RHCLK5 |UNUSED | |1 | | | | | | | | | +|H13 |RGB<0> |IOB |IO_L06P_1/A6/RHCLK4/IRDY1|OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|H14 | | |GND | | | | | | | | | | | | +|J1 | | |GND | | | | | | | | | | | | +|J2 | | |VCCO_3 | | |3 | | | | |2.50 | | | | +|J3 | |DIFFS |IO |UNUSED | |3 | | | | | | | | | +|J12 | |DIFFS |IO_L04N_1/A9/RHCLK1 |UNUSED | |1 | | | | | | | | | +|J13 |RGB<1> |IOB |IO_L05P_1/A8/RHCLK2 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|J14 |HS |IOB |IO_L05N_1/A7/RHCLK3/TRDY1|OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|K1 | | |VCCAUX | | | | | | | |2.5 | | | | +|K2 | | |NC | | | | | | | | | | | | +|K3 | |IOB |IO/VREF_3 |UNUSED | |3 | | | | | | | | | +|K12 | | |GND | | | | | | | | | | | | +|K13 |VS |IOB |IO/VREF_1 |OUTPUT |LVCMOS33 |1 |8 |FAST |NONE** | | |LOCATED |NO |NONE | +|K14 | |DIFFM |IO_L04P_1/A10/RHCLK0 |UNUSED | |1 | | | | | | | | | +|L1 | |DIFFM |IO_L08P_3 |UNUSED | |3 | | | | | | | | | +|L2 | |DIFFS |IO_L08N_3 |UNUSED | |3 | | | | | | | | | +|L3 | |DIFFM |IO_L09P_3 |UNUSED | |3 | | | | | | | | | +|L12 | | |VCCINT | | | | | | | |1.2 | | | | +|L13 | |DIFFM |IO_L03P_1/A12 |UNUSED | |1 | | | | | | | | | +|L14 | |DIFFS |IO_L03N_1/A11 |UNUSED | |1 | | | | | | | | | +|M1 | |DIFFS |IO_L09N_3 |UNUSED | |3 | | | | | | | | | +|M2 | |DIFFM |IO_L01P_2/CSO_B |UNUSED | |2 | | | | | | | | | +|M3 | | |GND | | | | | | | | | | | | +|M4 | |DIFFM |IO_L03P_2/D7/GCLK12 |UNUSED | |2 | | | | | | | | | +|M5 |LED<0> |IOB |IO_L04P_2/D4/GCLK14 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|M6 |CLK |IBUF |IP_L05P_2/RDWR_B/GCLK0 |INPUT |LVCMOS25* |2 | | | |NONE | |LOCATED |NO |NONE | +|M7 | | |GND | | | | | | | | | | | | +|M8 | | |VCCO_2 | | |2 | | | | |2.50 | | | | +|M9 | |DIFFS |IO_L08N_2/A22 |UNUSED | |2 | | | | | | | | | +|M10 | |DIFFS |IO_L09N_2/A20 |UNUSED | |2 | | | | | | | | | +|M11 |LED<1> |IOB |IO_L10N_2/VS1/A18 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|M12 | |DIFFM |IO_L02P_1/A14 |UNUSED | |1 | | | | | | | | | +|M13 | |DIFFS |IO_L02N_1/A13 |UNUSED | |1 | | | | | | | | | +|M14 | | |VCCO_1 | | |1 | | | | |3.30 | | | | +|N1 | |DIFFS |IO_L01N_2/INIT_B |UNUSED | |2 | | | | | | | | | +|N2 | |DIFFS |IO_L02N_2/MOSI/CSI_B |UNUSED | |2 | | | | | | | | | +|N3 | |DIFFSI |IP/VREF_2 |UNUSED | |2 | | | | | | | | | +|N4 |LED<5> |IOB |IO_L03N_2/D6/GCLK13 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|N5 |LED<4> |IOB |IO_L04N_2/D3/GCLK15 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|N6 | |DIFFSI |IP_L05N_2/M2/GCLK1 |UNUSED | |2 | | | | | | | | | +|N7 | |IOB |IO/M1 |UNUSED | |2 | | | | | | | | | +|N8 | |DIFFS |IO_L07N_2/DIN/D0 |UNUSED | |2 | | | | | | | | | +|N9 | |DIFFM |IO_L08P_2/A23 |UNUSED | |2 | | | | | | | | | +|N10 | |DIFFM |IO_L09P_2/A21 |UNUSED | |2 | | | | | | | | | +|N11 | |DIFFM |IO_L10P_2/VS2/A19 |UNUSED | |2 | | | | | | | | | +|N12 | |DIFFS |IO_L11N_2/CCLK |UNUSED | |2 | | | | | | | | | +|N13 | |DIFFM |IO_L01P_1/A16 |UNUSED | |1 | | | | | | | | | +|N14 | |DIFFS |IO_L01N_1/A15 |UNUSED | |1 | | | | | | | | | +|P1 | |DIFFM |IO_L02P_2/DOUT/BUSY |UNUSED | |2 | | | | | | | | | +|P2 | | |VCCINT | | | | | | | |1.2 | | | | +|P3 | | |VCCO_2 | | |2 | | | | |2.50 | | | | +|P4 |LED<6> |IOB |IO/D5 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|P5 | | |GND | | | | | | | | | | | | +|P6 |LED<3> |IOB |IO_L06P_2/D2/GCLK2 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|P7 |LED<2> |IOB |IO_L06N_2/D1/GCLK3 |OUTPUT |LVCMOS25* |2 |12 |SLOW |NONE** | | |LOCATED |NO |NONE | +|P8 | |DIFFM |IO_L07P_2/M0 |UNUSED | |2 | | | | | | | | | +|P9 | | |VCCAUX | | | | | | | |2.5 | | | | +|P10 | | |GND | | | | | | | | | | | | +|P11 | |IOB |IO/VREF_2 |UNUSED | |2 | | | | | | | | | +|P12 | |DIFFM |IO_L11P_2/VS0/A17 |UNUSED | |2 | | | | | | | | | +|P13 | | |DONE | | | | | | | | | | | | +|P14 | | |GND | | | | | | | | | | | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/main_par.xrpt b/main_par.xrpt new file mode 100644 index 0000000..d2af353 --- /dev/null +++ b/main_par.xrpt @@ -0,0 +1,1119 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + + +
+
+
+ + + +
+ + + + diff --git a/main_summary.html b/main_summary.html new file mode 100644 index 0000000..d0c4a9d --- /dev/null +++ b/main_summary.html @@ -0,0 +1,189 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
main Project Status (02/21/2013 - 20:21:36)
Project File:pong.xiseParser Errors: No Errors
Module Name:mainImplementation State:Programming File Generated
Target Device:xc3s250e-5cp132
  • Errors:
 +No Errors
Product Version:ISE 14.1
  • Warnings:
4 Warnings (0 new)
Design Goal:Balanced
  • Routing Results:
 +All Signals Completely Routed
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 +All Constraints Met
Environment: + +System Settings +
  • Final Timing Score:
0  (Timing Report)
+ + + + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers474,8961% 
    Number used as Flip Flops45   
    Number used as Latches2   
Number of 4 input LUTs584,8961% 
Number of occupied Slices522,4482% 
    Number of Slices containing only related logic5252100% 
    Number of Slices containing unrelated logic0520% 
Total Number of 4 input LUTs924,8961% 
    Number used as logic58   
    Number used as a route-thru34   
Number of bonded IOBs199220% 
Number of BUFGMUXs1244% 
Average Fanout of Non-Clock Nets2.67   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints: +All Constraints Met  
+ + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentThu Feb 21 20:21:01 201303 Warnings (0 new)5 Infos (0 new)
Translation ReportCurrentThu Feb 21 20:21:06 2013000
Map ReportCurrentThu Feb 21 20:21:11 2013001 Info (0 new)
Place and Route ReportCurrentThu Feb 21 20:21:23 201301 Warning (0 new)2 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentThu Feb 21 20:21:27 2013006 Infos (0 new)
Bitgen ReportCurrentThu Feb 21 20:21:32 2013000
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentThu Feb 21 20:21:32 2013
WebTalk Log FileCurrentThu Feb 21 20:21:36 2013
+ + +
Date Generated: 02/21/2013 - 20:21:36
+ \ No newline at end of file diff --git a/main_summary.xml b/main_summary.xml new file mode 100644 index 0000000..7f94188 --- /dev/null +++ b/main_summary.xml @@ -0,0 +1,10 @@ + + + + + + diff --git a/main_usage.xml b/main_usage.xml new file mode 100644 index 0000000..fa23101 --- /dev/null +++ b/main_usage.xml @@ -0,0 +1,452 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/main_vhdl.prj b/main_vhdl.prj new file mode 100644 index 0000000..645d869 --- /dev/null +++ b/main_vhdl.prj @@ -0,0 +1,2 @@ +vhdl work "C:\fpga\pong\vga.vhd" +vhdl work "C:\fpga\pong\main.vhd" diff --git a/main_xst.xrpt b/main_xst.xrpt new file mode 100644 index 0000000..8dc415b --- /dev/null +++ b/main_xst.xrpt @@ -0,0 +1,212 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
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+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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+ + + +
+ + + diff --git a/mainpins.ucf b/mainpins.ucf new file mode 100644 index 0000000..e69de29 diff --git a/pins.ucf b/pins.ucf new file mode 100644 index 0000000..9e56910 --- /dev/null +++ b/pins.ucf @@ -0,0 +1,24 @@ +NET "CLK" LOC = "M6"; + +NET "LED<0>" LOC = "M5"; +NET "LED<1>" LOC = "M11"; +NET "LED<2>" LOC = "P7"; +NET "LED<3>" LOC = "P6"; +NET "LED<4>" LOC = "N5"; +NET "LED<5>" LOC = "N4"; +NET "LED<6>" LOC = "P4"; +NET "LED<7>" LOC = "G1"; + +NET "RGB<7>" LOC = "F13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "RGB<6>" LOC = "D13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "RGB<5>" LOC = "C14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; + +NET "RGB<4>" LOC = "G14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "RGB<3>" LOC = "G13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "RGB<2>" LOC = "F14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; + +NET "RGB<1>" LOC = "J13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "RGB<0>" LOC = "H13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; + +NET "HS" LOC = "J14" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; +NET "VS" LOC = "K13" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = FAST; \ No newline at end of file diff --git a/pong.gise b/pong.gise new file mode 100644 index 0000000..b8604a9 --- /dev/null +++ b/pong.gise @@ -0,0 +1,188 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pong.xise b/pong.xise new file mode 100644 index 0000000..bbef0ff --- /dev/null +++ b/pong.xise @@ -0,0 +1,349 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/usage_statistics_webtalk.html b/usage_statistics_webtalk.html new file mode 100644 index 0000000..124209f --- /dev/null +++ b/usage_statistics_webtalk.html @@ -0,0 +1,1105 @@ +Device Usage Statistics Report + +

Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Version and Target Device
Product Version:ISE:14.1 (WebPack) - P.15xfTarget Family:Spartan3E
OS Platform:NTTarget Device:xc3s250e
Project ID (random number)80ba5fe55946451bba1c27089be4c561.7EC662CDC4744D03A066C93D40613B74.58Target Package:cp132
Registration ID__0_0_0Target Speed:-5
Date Generated2013-02-21T20:21:32Tool FlowISE
+ 
+ + + + + + + + + + + + + + +
User Environment
OS NameMicrosoft Windows 7 , 64-bitOS Releasemajor release (build 7600)
CPU NameIntel(R) Core(TM) i3 CPU 550 @ 3.20GHzCPU Speed3191 MHz
+ 
+ + + + + + + + + + + + +
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
+Adders/Subtractors=4 +
    +
  • 10-bit adder=2
    • +
  • 10-bit subtractor=2
    • +
+ +Comparators=12 +
    +
  • 11-bit comparator greatequal=4
    • +
  • 11-bit comparator greater=2
    • +
  • 11-bit comparator less=4
    • +
  • 11-bit comparator lessequal=2
    • +
+ +Counters=2 +
    +
  • 10-bit up counter=2
    • +
+ +Latches=1 +
    +
  • 8-bit latch=1
    • +
+ +Registers=31 +
    +
  • Flip-Flops=31
    • +
+ +		 +MiscellaneousStatistics +
    +
  • AGG_BONDED_IO=19
    • +
  • AGG_IO=19
    • +
  • AGG_SLICE=52
    • +
  • NUM_4_INPUT_LUT=92
    • +
  • NUM_BONDED_IBUF=1
    • +
  • NUM_BONDED_IOB=18
    • +
  • NUM_BUFGMUX=1
    • +
  • NUM_CYMUX=45
    • +
  • NUM_LUT_RT=34
    • +
  • NUM_SLICEL=52
    • +
  • NUM_SLICE_FF=45
    • +
  • NUM_SLICE_LATCH=2
    • +
  • NUM_XOR=50
    • +
+ +		 +NetStatistics +
    +
  • NumNets_Active=134
    • +
  • NumNets_Gnd=1
    • +
  • NumNets_Vcc=1
    • +
  • NumNodesOfType_Active_CLKPIN=27
    • +
  • NumNodesOfType_Active_CNTRLPIN=29
    • +
  • NumNodesOfType_Active_DOUBLE=151
    • +
  • NumNodesOfType_Active_DUMMY=213
    • +
  • NumNodesOfType_Active_DUMMYESC=1
    • +
  • NumNodesOfType_Active_GLOBAL=14
    • +
  • NumNodesOfType_Active_HFULLHEX=1
    • +
  • NumNodesOfType_Active_HUNIHEX=2
    • +
  • NumNodesOfType_Active_INPUT=246
    • +
  • NumNodesOfType_Active_IOBOUTPUT=1
    • +
  • NumNodesOfType_Active_OMUX=111
    • +
  • NumNodesOfType_Active_OUTPUT=114
    • +
  • NumNodesOfType_Active_PREBXBY=52
    • +
  • NumNodesOfType_Active_VFULLHEX=7
    • +
  • NumNodesOfType_Active_VLONG=1
    • +
  • NumNodesOfType_Active_VUNIHEX=6
    • +
  • NumNodesOfType_Gnd_DOUBLE=10
    • +
  • NumNodesOfType_Gnd_INPUT=12
    • +
  • NumNodesOfType_Gnd_OMUX=6
    • +
  • NumNodesOfType_Gnd_OUTPUT=8
    • +
  • NumNodesOfType_Gnd_PREBXBY=5
    • +
+ +SiteStatistics +
    +
  • IBUF-DIFFMI=1
    • +
  • IOB-DIFFM=8
    • +
  • IOB-DIFFS=9
    • +
  • SLICEL-SLICEM=21
    • +
+ +		 +SiteSummary +
    +
  • BUFGMUX=1
    • +
  • BUFGMUX_GCLKMUX=1
    • +
  • BUFGMUX_GCLK_BUFFER=1
    • +
  • IBUF=1
    • +
  • IBUF_INBUF=1
    • +
  • IBUF_PAD=1
    • +
  • IOB=18
    • +
  • IOB_OUTBUF=18
    • +
  • IOB_PAD=18
    • +
  • SLICEL=52
    • +
  • SLICEL_C1VDD=7
    • +
  • SLICEL_C2VDD=2
    • +
  • SLICEL_CYMUXF=25
    • +
  • SLICEL_CYMUXG=20
    • +
  • SLICEL_F=48
    • +
  • SLICEL_F5MUX=3
    • +
  • SLICEL_FFX=22
    • +
  • SLICEL_FFY=25
    • +
  • SLICEL_G=44
    • +
  • SLICEL_GNDF=18
    • +
  • SLICEL_GNDG=18
    • +
  • SLICEL_XORF=25
    • +
  • SLICEL_XORG=25
    • +
+ +
+ 
+ + + + + + + + +
Configuration Data
+BUFGMUX +
    +
  • S=[S_INV:1] [S:0]
    • +
+ +BUFGMUX_GCLKMUX +
    +
  • DISABLE_ATTR=[LOW:1]
    • +
  • S=[S_INV:1] [S:0]
    • +
+ +IBUF_PAD +
    +
  • IOATTRBOX=[LVCMOS25:1]
    • +
+ +IOB +
    +
  • O1=[O1_INV:0] [O1:18]
    • +
+ +IOB_OUTBUF +
    +
  • IN=[IN_INV:0] [IN:18]
    • +
+ +IOB_PAD +
    +
  • DRIVEATTRBOX=[8:10] [12:8]
    • +
  • IOATTRBOX=[LVCMOS25:8] [LVCMOS33:10]
    • +
  • SLEW=[SLOW:8] [FAST:10]
    • +
+		 + +SLICEL +
    +
  • BX=[BX_INV:0] [BX:8]
    • +
  • BY=[BY:3] [BY_INV:0]
    • +
  • CE=[CE:15] [CE_INV:0]
    • +
  • CIN=[CIN_INV:0] [CIN:20]
    • +
  • CLK=[CLK:25] [CLK_INV:2]
    • +
  • SR=[SR:14] [SR_INV:0]
    • +
+ +SLICEL_CYMUXF +
    +
  • 0=[0:25] [0_INV:0]
    • +
  • 1=[1_INV:0] [1:25]
    • +
+ +SLICEL_CYMUXG +
    +
  • 0=[0:20] [0_INV:0]
    • +
+		 + +SLICEL_F5MUX +
    +
  • S0=[S0:3] [S0_INV:0]
    • +
+ +SLICEL_FFX +
    +
  • CE=[CE:15] [CE_INV:0]
    • +
  • CK=[CK:21] [CK_INV:1]
    • +
  • D=[D:22] [D_INV:0]
    • +
  • FFX_INIT_ATTR=[INIT0:22]
    • +
  • FFX_SR_ATTR=[SRLOW:22]
    • +
  • LATCH_OR_FF=[FF:21] [LATCH:1]
    • +
  • SR=[SR:10] [SR_INV:0]
    • +
  • SYNC_ATTR=[ASYNC:12] [SYNC:10]
    • +
+		 + +SLICEL_FFY +
    +
  • CE=[CE:15] [CE_INV:0]
    • +
  • CK=[CK:24] [CK_INV:1]
    • +
  • D=[D:25] [D_INV:0]
    • +
  • FFY_INIT_ATTR=[INIT0:24] [INIT1:1]
    • +
  • FFY_SR_ATTR=[SRLOW:24] [SRHIGH:1]
    • +
  • LATCH_OR_FF=[FF:24] [LATCH:1]
    • +
  • SR=[SR:14] [SR_INV:0]
    • +
  • SYNC_ATTR=[ASYNC:11] [SYNC:14]
    • +
+ +SLICEL_XORF +
    +
  • 1=[1_INV:0] [1:25]
    • +
+		 + +
+ 
+ + + + + + + +
Pin Data
+BUFGMUX +
    +
  • I0=1
    • +
  • O=1
    • +
  • S=1
    • +
+ +BUFGMUX_GCLKMUX +
    +
  • I0=1
    • +
  • OUT=1
    • +
  • S=1
    • +
+ +BUFGMUX_GCLK_BUFFER +
    +
  • IN=1
    • +
  • OUT=1
    • +
+ +IBUF +
    +
  • I=1
    • +
  • PAD=1
    • +
+ +IBUF_INBUF +
    +
  • IN=1
    • +
  • OUT=1
    • +
+ +IBUF_PAD +
    +
  • PAD=1
    • +
+ +IOB +
    +
  • O1=18
    • +
  • PAD=18
    • +
+ +IOB_OUTBUF +
    +
  • IN=18
    • +
  • OUT=18
    • +
+ +IOB_PAD +
    +
  • PAD=18
    • +
+ +SLICEL +
    +
  • BX=8
    • +
  • BY=3
    • +
  • CE=15
    • +
  • CIN=20
    • +
  • CLK=27
    • +
  • COUT=20
    • +
  • F1=46
    • +
  • F2=23
    • +
  • F3=23
    • +
  • F4=19
    • +
  • G1=44
    • +
  • G2=22
    • +
  • G3=20
    • +
  • G4=15
    • +
  • SR=14
    • +
  • X=26
    • +
  • XQ=22
    • +
  • Y=20
    • +
  • YQ=25
    • +
+		 + +SLICEL_C1VDD +
    +
  • 1=7
    • +
+ +SLICEL_C2VDD +
    +
  • 1=2
    • +
+ +SLICEL_CYMUXF +
    +
  • 0=25
    • +
  • 1=25
    • +
  • OUT=25
    • +
  • S0=25
    • +
+ +SLICEL_CYMUXG +
    +
  • 0=20
    • +
  • 1=20
    • +
  • OUT=20
    • +
  • S0=20
    • +
+ +SLICEL_F +
    +
  • A1=46
    • +
  • A2=23
    • +
  • A3=23
    • +
  • A4=19
    • +
  • D=48
    • +
+ +SLICEL_F5MUX +
    +
  • F=3
    • +
  • G=3
    • +
  • OUT=3
    • +
  • S0=3
    • +
+		 + +SLICEL_FFX +
    +
  • CE=15
    • +
  • CK=22
    • +
  • D=22
    • +
  • Q=22
    • +
  • SR=10
    • +
+ +SLICEL_FFY +
    +
  • CE=15
    • +
  • CK=25
    • +
  • D=25
    • +
  • Q=25
    • +
  • SR=14
    • +
+ +SLICEL_G +
    +
  • A1=44
    • +
  • A2=22
    • +
  • A3=20
    • +
  • A4=15
    • +
  • D=44
    • +
+ +SLICEL_GNDF +
    +
  • 0=18
    • +
+ +SLICEL_GNDG +
    +
  • 0=18
    • +
+ +SLICEL_XORF +
    +
  • 0=25
    • +
  • 1=25
    • +
  • O=25
    • +
+		 + +SLICEL_XORG +
    +
  • 0=25
    • +
  • 1=25
    • +
  • O=25
    • +
+ +
+ 
+ + +
Tool Usage
Command Line History
    +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
  • xst -intstyle ise -ifn <ise_file>
    • +
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s250e-cp132-5 <fname>.ngc <fname>.ngd
    • +
  • map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
    • +
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
    • +
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
    • +
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
    • +
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
bitgen606000000
map616000000
ngdbuild626200000
par606000000
trce606000000
xst878700000
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Project Statistics
PROPEXT_xilxSynthMaxFanout_virtex2=100000PROP_Enable_Message_Filtering=false
PROP_FitterReportFormat=HTMLPROP_LastAppliedGoal=Balanced
PROP_LastAppliedStrategy=Xilinx Default (unlocked)PROP_ManualCompileOrderImp=false
PROP_PropSpecInProjFile=Store all valuesPROP_Simulator=ISim (VHDL/Verilog)
PROP_SynthTopFile=changedPROP_Top_Level_Module_Type=HDL
PROP_UseSmartGuide=falsePROP_UserConstraintEditorPreference=Text Editor
PROP_intProjectCreationTimestamp=2013-02-15T19:54:09PROP_intWbtProjectID=7EC662CDC4744D03A066C93D40613B74
PROP_intWbtProjectIteration=58PROP_intWorkingDirLocWRTProjDir=Same
PROP_intWorkingDirUsed=NoPROP_lockPinsUcfFile=changed
PROP_xilxBitgStart_IntDone=truePROP_AutoTop=false
PROP_DevFamily=Spartan3EPROP_DevDevice=xc3s250e
PROP_DevFamilyPMName=spartan3ePROP_DevPackage=cp132
PROP_Synthesis_Tool=XST (VHDL/Verilog)PROP_DevSpeed=-5
PROP_PreferredLanguage=VerilogFILE_UCF=1
FILE_VHDL=2
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BUFGP=1NGDBUILD_NUM_FD=1NGDBUILD_NUM_FDE=20NGDBUILD_NUM_FDR=13
NGDBUILD_NUM_FDRE=10NGDBUILD_NUM_FDS=1NGDBUILD_NUM_GND=1NGDBUILD_NUM_INV=11
NGDBUILD_NUM_LD=2NGDBUILD_NUM_LUT1=33NGDBUILD_NUM_LUT2=1NGDBUILD_NUM_LUT2_L=1
NGDBUILD_NUM_LUT3=6NGDBUILD_NUM_LUT3_L=3NGDBUILD_NUM_LUT4=29NGDBUILD_NUM_LUT4_D=1
NGDBUILD_NUM_LUT4_L=4NGDBUILD_NUM_MUXCY=45NGDBUILD_NUM_MUXF5=3NGDBUILD_NUM_OBUF=18
NGDBUILD_NUM_VCC=1NGDBUILD_NUM_XORCY=50
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BUFG=1NGDBUILD_NUM_FD=1NGDBUILD_NUM_FDE=20NGDBUILD_NUM_FDR=13
NGDBUILD_NUM_FDRE=10NGDBUILD_NUM_FDS=1NGDBUILD_NUM_GND=1NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=11NGDBUILD_NUM_LD=2NGDBUILD_NUM_LUT1=33NGDBUILD_NUM_LUT2=1
NGDBUILD_NUM_LUT2_L=1NGDBUILD_NUM_LUT3=6NGDBUILD_NUM_LUT3_L=3NGDBUILD_NUM_LUT4=29
NGDBUILD_NUM_LUT4_D=1NGDBUILD_NUM_LUT4_L=4NGDBUILD_NUM_MUXCY=45NGDBUILD_NUM_MUXF5=3
NGDBUILD_NUM_OBUF=18NGDBUILD_NUM_VCC=1NGDBUILD_NUM_XORCY=50
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj-ifmt=mixed-ofn=<design_top>-ofmt=NGC
-p=xc3s250e-5-cp132-top=<design_top>-opt_mode=Speed-opt_level=1
-iuc=NO-keep_hierarchy=No-netlist_hierarchy=As_Optimized-rtlview=Yes
-glob_opt=AllClockNets-read_cores=YES-write_timing_constraints=NO-cross_clock_analysis=NO
-bus_delimiter=<>-slice_utilization_ratio=100-bram_utilization_ratio=100-verilog2001=YES
-fsm_extract=YES-fsm_encoding=Auto-safe_implementation=No-fsm_style=LUT
-ram_extract=Yes-ram_style=Auto-rom_extract=Yes-shreg_extract=YES
-rom_style=Auto-auto_bram_packing=NO-resource_sharing=YES-async_to_sync=NO
-mult_style=Auto-iobuf=YES-max_fanout=100000-bufg=24
-register_duplication=YES-register_balancing=No-optimize_primitives=NO-use_clock_enable=Yes
-use_sync_set=Yes-use_sync_reset=Yes-iob=Auto-equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5
+ 
diff --git a/vga.vhd b/vga.vhd new file mode 100644 index 0000000..c9c01fb --- /dev/null +++ b/vga.vhd @@ -0,0 +1,69 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.STD_LOGIC_ARITH.ALL; +use IEEE.STD_LOGIC_UNSIGNED.ALL; + +entity vga is + port ( + CLK : in std_logic; + + LED : out std_logic_vector(7 downto 0); + + IRGB : in std_logic_vector(7 downto 0); + RGB : out std_logic_vector(7 downto 0); + + W : out std_logic; + X : out std_logic_vector(9 downto 0); + Y : out std_logic_vector(9 downto 0); + + HS : out std_logic; + VS : out std_logic + ); +end vga; + +architecture Behavioral of vga is + signal horiz : std_logic_vector(9 downto 0); + signal vert : std_logic_vector(9 downto 0); +begin + +process (CLK) begin + if CLK'event and CLK = '1' then + -- 144 and 784 + if (horiz >= 146) and (horiz < 788) + -- 39 and 519 + and (vert >= 32) and (vert < 519) then + W <= '1'; + RGB <= IRGB; + X <= horiz - 144 + 1; + Y <= vert - 39 + 1; + else + W <= '0'; + RGB <= "11100011"; + end if; + + if (horiz > 0) and (horiz < 97) then + HS <= '0'; + else + HS <= '1'; + end if; + + if (vert > 0) and (vert < 3) then + VS <= '0'; + else + VS <= '1'; + end if; + + horiz <= horiz + 1; + if (horiz = 800) then + vert <= vert + 1; + horiz <= (others => '0'); + end if; + + if (vert = 521) then + vert <= (others => '0'); + end if; + end if; +end process; + +end Behavioral; + diff --git a/vga_summary.html b/vga_summary.html new file mode 100644 index 0000000..3267f60 --- /dev/null +++ b/vga_summary.html @@ -0,0 +1,82 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
main Project Status (02/16/2013 - 01:50:51)
Project File:pong.xiseParser Errors: No Errors
Module Name:vgaImplementation State:Programming File Not Generated
Target Device:xc3s250e-5cp132
  • Errors:
 
Product Version:ISE 14.1
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentSat Feb 16 01:50:46 2013
WebTalk Log FileCurrentSat Feb 16 01:50:50 2013
+ + +
Date Generated: 02/16/2013 - 01:50:51
+ \ No newline at end of file diff --git a/vgapins.ucf b/vgapins.ucf new file mode 100644 index 0000000..e69de29 diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100644 index 0000000..a0c1d6c --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,45 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + diff --git a/xlnx_auto_0_xdb/cst.xbcd b/xlnx_auto_0_xdb/cst.xbcd new file mode 100644 index 0000000..fa02ec0 Binary files /dev/null and b/xlnx_auto_0_xdb/cst.xbcd differ diff --git a/xst/work/hdllib.ref b/xst/work/hdllib.ref new file mode 100644 index 0000000..523b2ca --- /dev/null +++ b/xst/work/hdllib.ref @@ -0,0 +1,4 @@ +AR vga behavioral C:/fpga/pong/vga.vhd sub00/vhpl03 1361499657 +AR main behavioral C:/fpga/pong/main.vhd sub00/vhpl01 1361499659 +EN main NULL C:/fpga/pong/main.vhd sub00/vhpl00 1361499658 +EN vga NULL C:/fpga/pong/vga.vhd sub00/vhpl02 1361499656 diff --git a/xst/work/hdpdeps.ref b/xst/work/hdpdeps.ref new file mode 100644 index 0000000..a9d28f7 --- /dev/null +++ b/xst/work/hdpdeps.ref @@ -0,0 +1,11 @@ +V3 7 +FL C:/fpga/pong/main.vhd 2013/02/21.18:24:26 P.15xf +EN work/main 1361499658 FL C:/fpga/pong/main.vhd PB ieee/std_logic_1164 1335251622 \ + PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625 +AR work/main/Behavioral 1361499659 \ + FL C:/fpga/pong/main.vhd EN work/main 1361499658 CP vga +FL C:/fpga/pong/vga.vhd 2013/02/21.20:20:49 P.15xf +EN work/vga 1361499656 FL C:/fpga/pong/vga.vhd PB ieee/std_logic_1164 1335251622 \ + PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625 +AR work/vga/Behavioral 1361499657 \ + FL C:/fpga/pong/vga.vhd EN work/vga 1361499656 diff --git a/xst/work/sub00/vhpl00.vho b/xst/work/sub00/vhpl00.vho new file mode 100644 index 0000000..13844a5 Binary files /dev/null and b/xst/work/sub00/vhpl00.vho differ diff --git a/xst/work/sub00/vhpl01.vho b/xst/work/sub00/vhpl01.vho new file mode 100644 index 0000000..6b53f49 Binary files /dev/null and b/xst/work/sub00/vhpl01.vho differ diff --git a/xst/work/sub00/vhpl02.vho b/xst/work/sub00/vhpl02.vho new file mode 100644 index 0000000..fc5e2ec Binary files /dev/null and b/xst/work/sub00/vhpl02.vho differ diff --git a/xst/work/sub00/vhpl03.vho b/xst/work/sub00/vhpl03.vho new file mode 100644 index 0000000..85903e6 Binary files /dev/null and b/xst/work/sub00/vhpl03.vho differ