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Release 14.1 Trace  (nt)
Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n
3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf

Design file:              main.ncd
Physical constraint file: main.pcf
Device,package,speed:     xc3s250e,cp132,-5 (PRODUCTION 1.27 2012-04-23)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter 
   value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock 
   Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 
   'Phase Error' calculations, these terms will be zero in the Clock 
   Uncertainty calculation.  Please make appropriate modification to 
   SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase 
   Error.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Clock CLK to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
HS          |    6.322(R)|CLK_BUFGP         |   0.000|
POUT        |    8.112(R)|CLK_BUFGP         |   0.000|
RGB<0>      |    6.754(R)|CLK_BUFGP         |   0.000|
RGB<1>      |    6.745(R)|CLK_BUFGP         |   0.000|
RGB<2>      |    7.196(R)|CLK_BUFGP         |   0.000|
RGB<3>      |    7.322(R)|CLK_BUFGP         |   0.000|
RGB<4>      |    6.975(R)|CLK_BUFGP         |   0.000|
RGB<5>      |    8.297(R)|CLK_BUFGP         |   0.000|
RGB<6>      |    8.081(R)|CLK_BUFGP         |   0.000|
RGB<7>      |    7.578(R)|CLK_BUFGP         |   0.000|
VS          |    6.132(R)|CLK_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock CLK
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
CLK            |    6.683|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Fri Feb 22 15:42:34 2013 
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Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 134 MB