]> Release 14.1 Trace (nt)Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf main.ncdmain.ncdmain.pcfmain.pcfxc3s250e-5PRODUCTION 1.27 2012-04-233INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.CLKCLKCLK6.683Fri Feb 22 15:42:34 2013 TraceTrace Settings Peak Memory Usage: 134 MB