main Project Status (02/22/2013 - 14:37:18)
Project File: pong.xise Parser Errors: No Errors
Module Name: main Implementation State: Programming File Generated
Target Device: xc3s250e-5cp132
  • Errors:
No Errors
Product Version:ISE 14.1
  • Warnings:
15 Warnings (15 new)
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
All Constraints Met
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Total Number Slice Registers 97 4,896 1%  
    Number used as Flip Flops 96      
    Number used as Latches 1      
Number of 4 input LUTs 376 4,896 7%  
Number of occupied Slices 249 2,448 10%  
    Number of Slices containing only related logic 249 249 100%  
    Number of Slices containing unrelated logic 0 249 0%  
Total Number of 4 input LUTs 450 4,896 9%  
    Number used as logic 376      
    Number used as a route-thru 74      
Number of bonded IOBs 19 92 20%  
Number of BUFGMUXs 2 24 8%  
Average Fanout of Non-Clock Nets 2.66      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFri Feb 22 14:36:37 2013015 Warnings (15 new)3 Infos (3 new)
Translation ReportCurrentFri Feb 22 14:36:43 2013000
Map ReportCurrentFri Feb 22 14:36:48 2013001 Info (0 new)
Place and Route ReportCurrentFri Feb 22 14:37:04 2013002 Infos (0 new)
Power Report     
Post-PAR Static Timing ReportCurrentFri Feb 22 14:37:07 2013006 Infos (0 new)
Bitgen ReportCurrentFri Feb 22 14:37:14 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateFri Feb 22 14:37:14 2013
WebTalk Log FileOut of DateFri Feb 22 14:37:18 2013

Date Generated: 02/22/2013 - 14:39:05