main Project Status (02/21/2013 - 20:21:36)
Project File:	pong.xise	Parser Errors:	No Errors
Module Name:	main	Implementation State:	Programming File Generated
Target Device:	xc3s250e-5cp132	Errors:	No Errors
Product Version:	ISE 14.1	Warnings:	4 Warnings (0 new)
Design Goal:	Balanced	Routing Results:	All Signals Completely Routed
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:	All Constraints Met
Environment:	System Settings	Final Timing Score:	0  (Timing Report)

 

Device Utilization Summary					[-]
Logic Utilization	Used	Available	Utilization	Note(s)
Total Number Slice Registers	47	4,896	1%
Number used as Flip Flops	45
Number used as Latches	2
Number of 4 input LUTs	58	4,896	1%
Number of occupied Slices	52	2,448	2%
Number of Slices containing only related logic	52	52	100%
Number of Slices containing unrelated logic	0	52	0%
Total Number of 4 input LUTs	92	4,896	1%
Number used as logic	58
Number used as a route-thru	34
Number of bonded IOBs	19	92	20%
Number of BUFGMUXs	1	24	4%
Average Fanout of Non-Clock Nets	2.67

 

Performance Summary				[-]
Final Timing Score:	0 (Setup: 0, Hold: 0)	Pinout Data:	Pinout Report
Routing Results:	All Signals Completely Routed	Clock Data:	Clock Report
Timing Constraints:	All Constraints Met

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report	Current	Thu Feb 21 20:21:01 2013	0	3 Warnings (0 new)	5 Infos (0 new)
Translation Report	Current	Thu Feb 21 20:21:06 2013	0	0	0
Map Report	Current	Thu Feb 21 20:21:11 2013	0	0	1 Info (0 new)
Place and Route Report	Current	Thu Feb 21 20:21:23 2013	0	1 Warning (0 new)	2 Infos (0 new)
Power Report
Post-PAR Static Timing Report	Current	Thu Feb 21 20:21:27 2013	0	0	6 Infos (0 new)
Bitgen Report	Current	Thu Feb 21 20:21:32 2013	0	0	0

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Thu Feb 21 20:21:32 2013
WebTalk Log File	Current	Thu Feb 21 20:21:36 2013

Date Generated: 02/21/2013 - 20:21:36