main Project Status (02/16/2013 - 01:50:51)
Project File:	pong.xise	Parser Errors:	No Errors
Module Name:	vga	Implementation State:	Programming File Not Generated
Target Device:	xc3s250e-5cp132	Errors:
Product Version:	ISE 14.1	Warnings:
Design Goal:	Balanced	Routing Results:
Design Strategy:	Xilinx Default (unlocked)	Timing Constraints:
Environment:		Final Timing Score:

 

Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
CPLD Fitter Report (Text)
Power Report
Post-PAR Static Timing Report
Bitgen Report

 

Secondary Reports			[-]
Report Name	Status	Generated
WebTalk Report	Current	Sat Feb 16 01:50:46 2013
WebTalk Log File	Current	Sat Feb 16 01:50:50 2013

Date Generated: 02/16/2013 - 01:50:51