213 lines
8 KiB
Text
213 lines
8 KiB
Text
Release 14.1 par P.15xf (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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ALECO-PC:: Fri Feb 22 15:42:14 2013
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par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
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Constraints file: main.pcf.
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Loading device for application Rf_Device from file '3s250e.nph' in environment C:\Xilinx\14.1\ISE_DS\ISE\.
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"main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5
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Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
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Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
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INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
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-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
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internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
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reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
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Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
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Device speed data version: "PRODUCTION 1.27 2012-04-23".
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Design Summary Report:
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Number of External IOBs 20 out of 92 21%
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Number of External Input IOBs 1
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Number of External Input IBUFs 1
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Number of LOCed External Input IBUFs 1 out of 1 100%
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Number of External Output IOBs 19
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Number of External Output IOBs 19
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Number of LOCed External Output IOBs 19 out of 19 100%
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Number of External Bidir IOBs 0
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Number of BUFGMUXs 2 out of 24 8%
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Number of Slices 318 out of 2448 12%
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Number of SLICEMs 0 out of 1224 0%
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Overall effort level (-ol): High
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Placer effort level (-pl): High
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Placer cost table entry (-t): 1
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Router effort level (-rl): High
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Starting initial Timing Analysis. REAL time: 1 secs
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Finished initial Timing Analysis. REAL time: 1 secs
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Starting Placer
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Total REAL time at the beginning of Placer: 1 secs
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Total CPU time at the beginning of Placer: 1 secs
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Phase 1.1 Initial Placement Analysis
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Phase 1.1 Initial Placement Analysis (Checksum:6a29e20) REAL time: 1 secs
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Phase 2.7 Design Feasibility Check
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Phase 2.7 Design Feasibility Check (Checksum:6a29e20) REAL time: 1 secs
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Phase 3.31 Local Placement Optimization
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Phase 3.31 Local Placement Optimization (Checksum:6a29e20) REAL time: 1 secs
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Phase 4.2 Initial Clock and IO Placement
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Phase 4.2 Initial Clock and IO Placement (Checksum:9fa8ca4e) REAL time: 2 secs
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Phase 5.30 Global Clock Region Assignment
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Phase 5.30 Global Clock Region Assignment (Checksum:9fa8ca4e) REAL time: 2 secs
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Phase 6.36 Local Placement Optimization
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Phase 6.36 Local Placement Optimization (Checksum:9fa8ca4e) REAL time: 2 secs
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Phase 7.8 Global Placement
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....................................
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..
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.............................................................................................
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..
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..
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Phase 7.8 Global Placement (Checksum:672c9b54) REAL time: 5 secs
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Phase 8.5 Local Placement Optimization
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Phase 8.5 Local Placement Optimization (Checksum:672c9b54) REAL time: 5 secs
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Phase 9.18 Placement Optimization
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Phase 9.18 Placement Optimization (Checksum:482ffdf2) REAL time: 5 secs
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Phase 10.5 Local Placement Optimization
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Phase 10.5 Local Placement Optimization (Checksum:482ffdf2) REAL time: 5 secs
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Total REAL time to Placer completion: 5 secs
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Total CPU time to Placer completion: 5 secs
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Writing design to file main.ncd
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Starting Router
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Phase 1 : 1798 unrouted; REAL time: 8 secs
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Phase 2 : 1669 unrouted; REAL time: 8 secs
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Phase 3 : 263 unrouted; REAL time: 8 secs
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Phase 4 : 342 unrouted; (Par is working to improve performance) REAL time: 9 secs
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Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
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Updating file: main.ncd with current fully routed design.
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Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
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Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 14 secs
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Updating file: main.ncd with current fully routed design.
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Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 14 secs
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Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
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Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
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Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
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Total REAL time to Router completion: 15 secs
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Total CPU time to Router completion: 14 secs
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Generating "PAR" statistics.
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**************************
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Generating Clock Report
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**************************
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+---------------------+--------------+------+------+------------+-------------+
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| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
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+---------------------+--------------+------+------+------------+-------------+
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| VGADriver/FRAME | BUFGMUX_X1Y10| No | 43 | 0.038 | 0.100 |
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+---------------------+--------------+------+------+------------+-------------+
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| CLK_BUFGP | BUFGMUX_X2Y1| No | 39 | 0.038 | 0.101 |
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+---------------------+--------------+------+------+------------+-------------+
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| VGADriver/W | Local| | 1 | 0.000 | 1.110 |
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+---------------------+--------------+------+------+------------+-------------+
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* Net Skew is the difference between the minimum and maximum routing
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only delays for the net. Note this is different from Clock Skew which
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is reported in TRCE timing report. Clock Skew is the difference between
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the minimum and maximum path delays which includes logic delays.
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* The fanout is the number of component pins not the individual BEL loads,
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for example SLICE loads not FF loads.
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Timing Score: 0 (Setup: 0, Hold: 0)
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Asterisk (*) preceding a constraint indicates it was not met.
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This may be due to a setup or hold violation.
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----------------------------------------------------------------------------------------------------------
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Constraint | Check | Worst Case | Best Case | Timing | Timing
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| | Slack | Achievable | Errors | Score
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net VGA | SETUP | N/A| 11.237ns| N/A| 0
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Driver/FRAME | HOLD | 0.850ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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Autotimespec constraint for clock net CLK | SETUP | N/A| 6.683ns| N/A| 0
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_BUFGP | HOLD | 0.892ns| | 0| 0
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----------------------------------------------------------------------------------------------------------
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All constraints were met.
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INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the
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constraint is not analyzed due to the following: No paths covered by this
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constraint; Other constraints intersect with this constraint; or This
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constraint was disabled by a Path Tracing Control. Please run the Timespec
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Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.
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Generating Pad Report.
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All signals are completely routed.
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Total REAL time to PAR completion: 15 secs
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Total CPU time to PAR completion: 15 secs
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Peak Memory Usage: 231 MB
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Placement: Completed - No errors found.
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Routing: Completed - No errors found.
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Number of error messages: 0
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Number of warning messages: 0
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Number of info messages: 1
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Writing design to file main.ncd
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PAR done!
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