pong/main_map.map

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Release 14.1 Map P.15xf (nt)
Xilinx Map Application Log File for Design 'main'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off
-c 100 -o main_map.ncd main.ngd main.pcf
Target Device : xc3s250e
Target Package : cp132
Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Fri Feb 22 15:42:09 2013
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Total Number Slice Registers: 146 out of 4,896 2%
Number used as Flip Flops: 145
Number used as Latches: 1
Number of 4 input LUTs: 508 out of 4,896 10%
Logic Distribution:
Number of occupied Slices: 318 out of 2,448 12%
Number of Slices containing only related logic: 318 out of 318 100%
Number of Slices containing unrelated logic: 0 out of 318 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 584 out of 4,896 11%
Number used as logic: 508
Number used as a route-thru: 76
The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 20 out of 92 21%
Number of BUFGMUXs: 2 out of 24 8%
Average Fanout of Non-Clock Nets: 2.78
Peak Memory Usage: 212 MB
Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "main_map.mrp" for details.