72 lines
2.6 KiB
Text
72 lines
2.6 KiB
Text
Release 14.1 Map P.15xf (nt)
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Xilinx Map Application Log File for Design 'main'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off
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-c 100 -o main_map.ncd main.ngd main.pcf
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Target Device : xc3s250e
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Target Package : cp132
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Target Speed : -5
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Mapper Version : spartan3e -- $Revision: 1.55 $
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Mapped Date : Fri Feb 22 15:42:09 2013
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Mapping design into LUTs...
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Running directed packing...
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Running delay-based LUT packing...
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Running related packing...
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Updating timing models...
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Design Summary
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--------------
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Design Summary:
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Number of errors: 0
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Number of warnings: 0
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Logic Utilization:
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Total Number Slice Registers: 146 out of 4,896 2%
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Number used as Flip Flops: 145
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Number used as Latches: 1
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Number of 4 input LUTs: 508 out of 4,896 10%
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Logic Distribution:
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Number of occupied Slices: 318 out of 2,448 12%
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Number of Slices containing only related logic: 318 out of 318 100%
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Number of Slices containing unrelated logic: 0 out of 318 0%
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*See NOTES below for an explanation of the effects of unrelated logic.
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Total Number of 4 input LUTs: 584 out of 4,896 11%
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Number used as logic: 508
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Number used as a route-thru: 76
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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Number of bonded IOBs: 20 out of 92 21%
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Number of BUFGMUXs: 2 out of 24 8%
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Average Fanout of Non-Clock Nets: 2.78
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Peak Memory Usage: 212 MB
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Total REAL time to MAP completion: 2 secs
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Total CPU time to MAP completion: 2 secs
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NOTES:
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Related logic is defined as being logic that shares connectivity - e.g. two
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LUTs are "related" if they share common inputs. When assembling slices,
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Map gives priority to combine logic that is related. Doing so results in
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the best timing performance.
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Unrelated logic shares no connectivity. Map will only begin packing
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unrelated logic into a slice once 99% of the slices are occupied through
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related logic packing.
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Note that once logic distribution reaches the 99% level through related
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logic packing, this does not mean the device is completely utilized.
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Unrelated logic packing will then begin, continuing until all usable LUTs
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and FFs are occupied. Depending on your timing budget, increased levels of
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unrelated logic packing may adversely affect the overall timing performance
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of your design.
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Mapping completed.
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See MAP report file "main_map.mrp" for details.
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