44 lines
801 B
VHDL
44 lines
801 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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-- period of 25 MHz oscillator is 40 ns
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entity speaker is
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port (
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CLK: in std_logic;
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HPERIOD: in std_logic_vector(24 downto 0);
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PLAY: in std_logic;
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PIN: out std_logic
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);
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end speaker;
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architecture Behavioral of speaker is
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begin
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process (CLK)
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variable sout: std_logic := '0';
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variable prescaler: std_logic_vector(24 downto 0) := (others => '0');
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begin
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if CLK'event and CLK = '1' then
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if PLAY = '1' then
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if prescaler >= HPERIOD then
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sout := not sout;
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prescaler := (others => '0');
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end if;
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prescaler := prescaler + 1;
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else
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sout := '0';
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prescaler := (others => '0');
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end if;
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end if;
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PIN <= sout;
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end process;
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end Behavioral;
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