74 lines
1.3 KiB
VHDL
74 lines
1.3 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity vga is
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port (
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CLK : in std_logic;
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IRGB : in std_logic_vector(7 downto 0);
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RGB : out std_logic_vector(7 downto 0);
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FRAME: out std_logic;
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W : out std_logic;
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X : out std_logic_vector(9 downto 0);
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Y : out std_logic_vector(9 downto 0);
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HS : out std_logic;
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VS : out std_logic
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);
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end vga;
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architecture Behavioral of vga is
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signal horiz : std_logic_vector(9 downto 0);
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signal vert : std_logic_vector(9 downto 0);
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begin
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process (CLK)
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variable fout : std_logic := '0';
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begin
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if CLK'event and CLK = '1' then
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if (horiz >= 145) and (horiz < 788)
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and (vert >= 35) and (vert < 514) then
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W <= '1';
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RGB <= IRGB;
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X <= horiz - 146 + 1;
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Y <= vert - 34 + 1;
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else
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W <= '0';
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RGB <= "00000000";
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end if;
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if (horiz > 0) and (horiz < 97) then
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HS <= '0';
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else
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HS <= '1';
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end if;
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if (vert > 0) and (vert < 3) then
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VS <= '0';
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else
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VS <= '1';
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end if;
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horiz <= horiz + 1;
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if (horiz = 800) then
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vert <= vert + 1;
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horiz <= (others => '0');
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end if;
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if (vert = 521) then
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fout := '1';
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vert <= (others => '0');
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else
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fout := '0';
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end if;
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FRAME <= fout;
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end if;
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end process;
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end Behavioral;
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