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init
2013-02-22 02:27:53 +00:00
Release 14.1 - xst P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
--> Reading design: main.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "main.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "main"
Output Format : NGC
Target Device : xc3s250e-5-cp132
---- Source Options
Top Module Name : main
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 100000
Add Generic Clock Buffer(BUFG) : 24
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work.
Entity <vga> compiled.
Entity <vga> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work.
Architecture behavioral of Entity main is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <main> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<w>, <x>, <y>
Entity <main> analyzed. Unit <main> generated.
Analyzing Entity <vga> in library <work> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <vga>.
Related source file is "C:/fpga/pong/vga.vhd".
WARNING:Xst:1305 - Output <LED> is never assigned. Tied to value 00000000.
Found 1-bit register for signal <HS>.
Found 1-bit register for signal <W>.
Found 10-bit register for signal <X>.
Found 10-bit register for signal <Y>.
Found 1-bit register for signal <VS>.
Found 8-bit register for signal <RGB>.
Found 10-bit up counter for signal <horiz>.
Found 11-bit comparator greater for signal <HS$cmp_gt0000> created at line 44.
Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 44.
Found 10-bit up counter for signal <vert>.
Found 11-bit comparator greater for signal <VS$cmp_gt0000> created at line 50.
Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 50.
Found 11-bit comparator greatequal for signal <W$cmp_ge0000> created at line 32.
Found 11-bit comparator greatequal for signal <W$cmp_ge0001> created at line 32.
Found 11-bit comparator less for signal <W$cmp_lt0000> created at line 32.
Found 11-bit comparator less for signal <W$cmp_lt0001> created at line 32.
Found 10-bit adder for signal <X$add0000> created at line 37.
Found 10-bit subtractor for signal <X$addsub0000> created at line 37.
Found 10-bit adder for signal <Y$add0000> created at line 38.
Found 10-bit subtractor for signal <Y$addsub0000> created at line 38.
Summary:
inferred 2 Counter(s).
inferred 31 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s).
inferred 8 Comparator(s).
Unit <vga> synthesized.
Synthesizing Unit <main>.
Related source file is "C:/fpga/pong/main.vhd".
WARNING:Xst:737 - Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0000> created at line 59.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0001> created at line 59.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0000> created at line 59.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0001> created at line 59.
Summary:
inferred 4 Comparator(s).
Unit <main> synthesized.
=========================================================================
HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
10-bit adder : 2
10-bit subtractor : 2
# Counters : 2
10-bit up counter : 2
# Registers : 6
1-bit register : 3
10-bit register : 2
8-bit register : 1
# Latches : 1
8-bit latch : 1
# Comparators : 12
11-bit comparator greatequal : 4
11-bit comparator greater : 2
11-bit comparator less : 4
11-bit comparator lessequal : 2
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# Adders/Subtractors : 4
10-bit adder : 2
10-bit subtractor : 2
# Counters : 2
10-bit up counter : 2
# Registers : 31
Flip-Flops : 31
# Latches : 1
8-bit latch : 1
# Comparators : 12
11-bit comparator greatequal : 4
11-bit comparator greater : 2
11-bit comparator less : 4
11-bit comparator lessequal : 2
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
INFO:Xst:2261 - The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 4 FFs/Latches, which will be removed : <6> <5> <1> <0>
INFO:Xst:2261 - The FF/Latch <4> in Unit <LPM_LATCH_1> is equivalent to the following 2 FFs/Latches, which will be removed : <3> <2>
Optimizing unit <main> ...
Optimizing unit <vga> ...
Mapping all equations...
Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_4> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <VGADriver/RGB_3> <VGADriver/RGB_2>
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 4 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_1> <VGADriver/RGB_0>
Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 2.
Final Macro Processing ...
=========================================================================
Final Register Report
Macro Statistics
# Registers : 45
Flip-Flops : 45
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : main.ngr
Top Level Output File Name : main
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 19
Cell Usage :
# BELS : 189
# GND : 1
# INV : 11
# LUT1 : 33
# LUT2 : 1
# LUT2_L : 1
# LUT3 : 6
# LUT3_L : 3
# LUT4 : 29
# LUT4_D : 1
# LUT4_L : 4
# MUXCY : 45
# MUXF5 : 3
# VCC : 1
# XORCY : 50
# FlipFlops/Latches : 47
# FD : 1
# FDE : 20
# FDR : 13
# FDRE : 10
# FDS : 1
# LD : 2
# Clock Buffers : 1
# BUFGP : 1
# IO Buffers : 18
# OBUF : 18
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s250ecp132-5
Number of Slices: 50 out of 2448 2%
Number of Slice Flip Flops: 47 out of 4896 0%
Number of 4 input LUTs: 89 out of 4896 1%
Number of IOs: 19
Number of bonded IOBs: 19 out of 92 20%
Number of GCLKs: 1 out of 24 4%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
VGADriver/W | NONE(inrgb_4) | 2 |
CLK | BUFGP | 45 |
-----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 5.905ns (Maximum Frequency: 169.349MHz)
Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.221ns
Maximum combinational path delay: No path found
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 5.905ns (frequency: 169.349MHz)
Total number of paths / destination ports: 1505 / 95
-------------------------------------------------------------------------
Delay: 5.905ns (Levels of Logic = 4)
Source: VGADriver/vert_6 (FF)
Destination: VGADriver/Y_9 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: VGADriver/vert_6 to VGADriver/Y_9
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDRE:C->Q 4 0.514 0.651 VGADriver/vert_6 (VGADriver/vert_6)
LUT2_L:I0->LO 1 0.612 0.103 VGADriver/vert_cmp_eq00001_SW0 (VGADriver/X_and000093)
LUT4:I3->O 3 0.612 0.454 VGADriver/vert_cmp_eq00001 (VGADriver/N7)
LUT4_D:I3->O 4 0.612 0.502 VGADriver/X_and0000136 (VGADriver/X_and0000136)
LUT4:I3->O 10 0.612 0.750 VGADriver/X_and0000151_2 (VGADriver/X_and0000151_1)
FDE:CE 0.483 VGADriver/Y_0
----------------------------------------
Total 5.905ns (3.445ns logic, 2.460ns route)
(58.3% logic, 41.7% route)
=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 10 / 10
-------------------------------------------------------------------------
Offset: 4.221ns (Levels of Logic = 1)
Source: VGADriver/RGB_7 (FF)
Destination: RGB<7> (PAD)
Source Clock: CLK rising
Data Path: VGADriver/RGB_7 to RGB<7>
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDS:C->Q 5 0.514 0.538 VGADriver/RGB_7 (VGADriver/RGB_7)
OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>)
----------------------------------------
Total 4.221ns (3.683ns logic, 0.538ns route)
(87.3% logic, 12.7% route)
=========================================================================
Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.42 secs
-->
Total memory usage is 217424 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered)
Number of infos : 5 ( 0 filtered)
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