69 lines
1.2 KiB
VHDL
69 lines
1.2 KiB
VHDL
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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use IEEE.STD_LOGIC_UNSIGNED.ALL;
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entity main is
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port (
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CLK : in std_logic;
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LED : out std_logic_vector(7 downto 0);
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RGB : out std_logic_vector(7 downto 0);
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HS : out std_logic;
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VS : out std_logic
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);
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end main;
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architecture Behavioral of main is
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component vga is
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port (
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CLK : in std_logic;
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LED : out std_logic_vector(7 downto 0);
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IRGB : in std_logic_vector(7 downto 0);
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RGB : out std_logic_vector(7 downto 0);
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W : out std_logic;
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X : out std_logic_vector(9 downto 0);
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Y : out std_logic_vector(9 downto 0);
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VS : out std_logic;
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HS : out std_logic
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);
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end component;
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signal inrgb : std_logic_vector(7 downto 0) := "00000000";
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signal w : std_logic;
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signal x : std_logic_vector(9 downto 0);
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signal y : std_logic_vector(9 downto 0);
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begin
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VGADriver : component vga port map (
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CLK => CLK,
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LED => LED,
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HS => HS,
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VS => VS,
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RGB => RGB,
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IRGB => inrgb,
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W => w,
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X => x,
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Y => y
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);
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process (CLK) begin
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if w = '1' then
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if x >= 300 and x <= 340 and y >= 220 and y <= 260 then
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inrgb <= "11100011";
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else
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inrgb <= "00011100";
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end if;
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end if;
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end process;
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end Behavioral;
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