79 lines
3.3 KiB
Text
79 lines
3.3 KiB
Text
--------------------------------------------------------------------------------
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Release 14.1 Trace (nt)
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Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
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C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n
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3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
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Design file: main.ncd
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Physical constraint file: main.pcf
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Device,package,speed: xc3s250e,cp132,-5 (PRODUCTION 1.27 2012-04-23)
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Report level: verbose report
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Environment Variable Effect
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-------------------- ------
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NONE No environment variables were set
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--------------------------------------------------------------------------------
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INFO:Timing:2698 - No timing constraints found, doing default enumeration.
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INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
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INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
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option. All paths that are not constrained will be reported in the
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unconstrained paths section(s) of the report.
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INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
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a 50 Ohm transmission line loading model. For the details of this model,
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and for more information on accounting for different loading conditions,
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please see the device datasheet.
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INFO:Timing:3390 - This architecture does not support a default System Jitter
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value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
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Uncertainty calculation.
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INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
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'Phase Error' calculations, these terms will be zero in the Clock
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Uncertainty calculation. Please make appropriate modification to
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SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
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Error.
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Data Sheet report:
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-----------------
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All values displayed in nanoseconds (ns)
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Clock CLK to Pad
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------------+------------+------------------+--------+
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| clk (edge) | | Clock |
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Destination | to PAD |Internal Clock(s) | Phase |
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------------+------------+------------------+--------+
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HS | 6.320(R)|CLK_BUFGP | 0.000|
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RGB<0> | 7.061(R)|CLK_BUFGP | 0.000|
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RGB<1> | 7.052(R)|CLK_BUFGP | 0.000|
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RGB<2> | 7.348(R)|CLK_BUFGP | 0.000|
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RGB<3> | 7.565(R)|CLK_BUFGP | 0.000|
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RGB<4> | 7.538(R)|CLK_BUFGP | 0.000|
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RGB<5> | 8.606(R)|CLK_BUFGP | 0.000|
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RGB<6> | 8.389(R)|CLK_BUFGP | 0.000|
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RGB<7> | 7.981(R)|CLK_BUFGP | 0.000|
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VS | 6.627(R)|CLK_BUFGP | 0.000|
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------------+------------+------------------+--------+
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Clock to Setup on destination clock CLK
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---------------+---------+---------+---------+---------+
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| Src:Rise| Src:Fall| Src:Rise| Src:Fall|
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Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
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---------------+---------+---------+---------+---------+
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CLK | 5.493| | | |
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---------------+---------+---------+---------+---------+
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Analysis completed Thu Feb 21 20:21:26 2013
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--------------------------------------------------------------------------------
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Trace Settings:
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-------------------------
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Trace Settings
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Peak Memory Usage: 129 MB
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