15 lines
181 B
VHDL
15 lines
181 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_1164.ALL;
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entity clockadjust is
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end clockadjust;
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architecture Behavioral of clockadjust is
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begin
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end Behavioral;
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