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actually wrote pong

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Alec Obradovich 2013-02-22 16:00:03 -06:00
parent ef1ee1e003
commit f002948680
57 changed files with 2676 additions and 1007 deletions
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21
PS2Driver.vhd Normal file
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@ -0,0 +1,21 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PS2Driver is
port (
CLK: in std_logic;
CLR: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
KEY: out std_logic_vector(15 downto 0);
);
end PS2Driver;
architecture Behavioral of PS2Driver is
begin
end Behavioral;

2
_ngo/netlist.lst
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@ -1,2 +1,2 @@
C:\fpga\pong\main.ngc 1361499661 C:\fpga\pong\main.ngc 1361569322
OK OK

4
_xmsgs/par.xmsgs
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@ -8,10 +8,6 @@
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;. <msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg> </msg>
<msg type="warning" file="Route" num="455" delta="old" >CLK Net:<arg fmt="%s" index="1">VGADriver/W</arg> may have excessive skew because
<arg fmt="%d" index="2">2</arg> CLK pins and <arg fmt="%d" index="3">0</arg> NON_CLK pins failed to route using a CLK template.
</msg>
<msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg> <msg type="info" file="Timing" num="2761" delta="old" >N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</msg>
</messages> </messages>

2
_xmsgs/pn_parser.xmsgs
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@ -8,7 +8,7 @@
<!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. --> <!-- Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. -->
<messages> <messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/fpga/pong/vga.vhd&quot; into library work</arg> <msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/fpga/pong/main.vhd&quot; into library work</arg>
</msg> </msg>
</messages> </messages>

185
_xmsgs/xst.xmsgs
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@ -5,26 +5,197 @@
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<messages> <messages>
<msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">C:/fpga/pong/main.vhd</arg>&quot; line <arg fmt="%d" index="2">57</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: <msg type="warning" file="Xst" num="819" delta="old" >&quot;<arg fmt="%s" index="1">C:/fpga/pong/main.vhd</arg>&quot; line <arg fmt="%d" index="2">85</arg>: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<arg fmt="%s" index="3">&lt;w&gt;, &lt;x&gt;, &lt;y&gt;</arg> <arg fmt="%s" index="3">&lt;w&gt;, &lt;y&gt;, &lt;x&gt;</arg>
</msg> </msg>
<msg type="warning" file="Xst" num="1305" delta="old" >Output &lt;<arg fmt="%s" index="1">LED</arg>&gt; is never assigned. Tied to value <arg fmt="%s" index="2">00000000</arg>. <msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">ph</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00100000</arg>.
</msg>
<msg type="warning" file="Xst" num="653" delta="old" >Signal &lt;<arg fmt="%s" index="1">cw</arg>&gt; is used but never assigned. This sourceless signal will be automatically connected to value <arg fmt="%s" index="2">00001010</arg>.
</msg> </msg>
<msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">inrgb</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. <msg type="warning" file="Xst" num="737" delta="old" >Found <arg fmt="%d" index="1">8</arg>-bit latch for signal &lt;<arg fmt="%s" index="2">inrgb</arg>&gt;. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
</msg> </msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LPM_LATCH_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;6&gt; &lt;5&gt; &lt;1&gt; &lt;0&gt; </arg> <msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_24</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg> </msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LPM_LATCH_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;3&gt; &lt;2&gt; </arg> <msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_23</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg> </msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">VGADriver/RGB_4</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">main</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">2 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;VGADriver/RGB_3&gt; &lt;VGADriver/RGB_2&gt; </arg> <msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_22</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg> </msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">VGADriver/RGB_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">main</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">4 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;VGADriver/RGB_6&gt; &lt;VGADriver/RGB_5&gt; &lt;VGADriver/RGB_1&gt; &lt;VGADriver/RGB_0&gt; </arg> <msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_21</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_20</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_19</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_18</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_17</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_16</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_15</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_14</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_13</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_10</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_9</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_8</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_7</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_6</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_4</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_24</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_23</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_22</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_21</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_20</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_19</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_18</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_17</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_16</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_15</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_14</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_13</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_10</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_9</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_8</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_7</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_6</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_5</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_4</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_3</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">hper_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">hper_11</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">main</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">FF/Latch</arg>, which will be removed : <arg fmt="%s" index="4">&lt;hper_12&gt; </arg>
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">LPM_LATCH_1</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;6&gt; &lt;5&gt; &lt;4&gt; &lt;3&gt; &lt;2&gt; &lt;1&gt; &lt;0&gt; </arg>
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdy_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdy_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_0</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_1</arg>&gt; has a constant value of <arg fmt="%d" index="2">0</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="warning" file="Xst" num="1293" delta="old" >FF/Latch &lt;<arg fmt="%s" index="1">cdx_2</arg>&gt; has a constant value of <arg fmt="%d" index="2">1</arg> in block &lt;<arg fmt="%s" index="3">main</arg>&gt;. This FF/Latch will be trimmed during the optimization process.
</msg>
<msg type="info" file="Xst" num="2261" delta="old" >The FF/Latch &lt;<arg fmt="%s" index="1">VGADriver/RGB_7</arg>&gt; in Unit &lt;<arg fmt="%s" index="2">main</arg>&gt; is equivalent to the following <arg fmt="%s" index="3">7 FFs/Latches</arg>, which will be removed : <arg fmt="%s" index="4">&lt;VGADriver/RGB_6&gt; &lt;VGADriver/RGB_5&gt; &lt;VGADriver/RGB_4&gt; &lt;VGADriver/RGB_3&gt; &lt;VGADriver/RGB_2&gt; &lt;VGADriver/RGB_1&gt; &lt;VGADriver/RGB_0&gt; </arg>
</msg> </msg>
<msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. <msg type="info" file="Xst" num="2169" delta="old" >HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

4
iseconfig/main.xreport
View file

@ -1,9 +1,9 @@
<?xml version='1.0' encoding='UTF-8'?> <?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" > <report-views version="2.0" >
<header> <header>
<DateModified>2013-02-18T14:32:38</DateModified> <DateModified>2013-02-21T22:39:36</DateModified>
<ModuleName>main</ModuleName> <ModuleName>main</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp> <SummaryTimeStamp>2013-02-21T20:50:16</SummaryTimeStamp>
<SavedFilePath>C:/fpga/pong/iseconfig/main.xreport</SavedFilePath> <SavedFilePath>C:/fpga/pong/iseconfig/main.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/fpga/pong\</ImplementationReportsDirectory> <ImplementationReportsDirectory>C:/fpga/pong\</ImplementationReportsDirectory>
<DateInitialized>2013-02-15T20:59:38</DateInitialized> <DateInitialized>2013-02-15T20:59:38</DateInitialized>

2
main.bgn
View file

@ -5,7 +5,7 @@ C:\Xilinx\14.1\ISE_DS\ISE\.
"main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5 "main" is an NCD, version 3.2, device xc3s250e, package cp132, speed -5
Opened constraints file main.pcf. Opened constraints file main.pcf.
Thu Feb 21 20:21:30 2013 Fri Feb 22 15:42:37 2013
C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No main.ncd C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g ConfigRate:1 -g ProgPin:PullUp -g DonePin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g DCMShutdown:Disable -g StartUpClk:CClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g DonePipe:Yes -g DriveDone:No main.ncd

BIN
main.bit
View file

Binary file not shown.

2
main.bld
View file

@ -26,7 +26,7 @@ NGDBUILD Design Results Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 0 Number of warnings: 0
Total memory usage is 129668 kilobytes Total memory usage is 131268 kilobytes
Writing NGD file "main.ngd" ... Writing NGD file "main.ngd" ...
Total REAL time to NGDBUILD completion: 3 sec Total REAL time to NGDBUILD completion: 3 sec

484
main.cmd_log
View file

@ -376,3 +376,487 @@ map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_ma
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd
xst -intstyle ise -ifn "C:/fpga/pong/main.xst" -ofn "C:/fpga/pong/main.syr"
ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc pins.ucf -p xc3s250e-cp132-5 main.ngc main.ngd
map -intstyle ise -p xc3s250e-cp132-5 -cm area -ir off -pr off -c 100 -o main_map.ncd main.ngd main.pcf
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
bitgen -intstyle ise -f main.ut main.ncd

2
main.drc
View file

@ -1,7 +1,7 @@
Release 14.1 Drc P.15xf (nt) Release 14.1 Drc P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Thu Feb 21 20:21:30 2013 Fri Feb 22 15:42:37 2013
drc -z main.ncd main.pcf drc -z main.ncd main.pcf

2
main.ncd
View file

File diff suppressed because one or more lines are too long

2
main.ngc
View file

File diff suppressed because one or more lines are too long

2
main.ngd
View file

File diff suppressed because one or more lines are too long

2
main.ngr
View file

File diff suppressed because one or more lines are too long

4
main.pad
View file

@ -1,7 +1,7 @@
Release 14.1 - par P.15xf (nt) Release 14.1 - par P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Thu Feb 21 20:21:23 2013 Fri Feb 22 15:42:30 2013
# NOTE: This file is designed to be imported into a spreadsheet program # NOTE: This file is designed to be imported into a spreadsheet program
@ -34,7 +34,7 @@ A12||DIFFS|IO_L02N_0|UNUSED||0|||||||||
A13||DIFFM|IO_L01P_0|UNUSED||0||||||||| A13||DIFFM|IO_L01P_0|UNUSED||0|||||||||
A14|||TDO|||||||||||| A14|||TDO||||||||||||
B1||DIFFS|IO_L01N_3|UNUSED||3||||||||| B1||DIFFS|IO_L01N_3|UNUSED||3|||||||||
B2||DIFFM|IO_L01P_3|UNUSED||3||||||||| B2|POUT|IOB|IO_L01P_3|OUTPUT|LVCMOS25*|3|12|SLOW|NONE**|||LOCATED|NO|NONE|
B3||DIFFS|IO_L11N_0/HSWAP|UNUSED||0||||||||| B3||DIFFS|IO_L11N_0/HSWAP|UNUSED||0|||||||||
B4||DIFFM|IO_L10P_0|UNUSED||0||||||||| B4||DIFFM|IO_L10P_0|UNUSED||0|||||||||
B5||DIFFM|IO_L09P_0|UNUSED||0||||||||| B5||DIFFM|IO_L09P_0|UNUSED||0|||||||||

94
main.par
View file

@ -1,7 +1,7 @@
Release 14.1 par P.15xf (nt) Release 14.1 par P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
ALECO-PC:: Thu Feb 21 20:21:13 2013 ALECO-PC:: Fri Feb 22 15:42:14 2013
par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf par -w -intstyle ise -ol high -t 1 main_map.ncd main.ncd main.pcf
@ -24,7 +24,7 @@ Device speed data version: "PRODUCTION 1.27 2012-04-23".
Design Summary Report: Design Summary Report:
Number of External IOBs 19 out of 92 20% Number of External IOBs 20 out of 92 21%
Number of External Input IOBs 1 Number of External Input IOBs 1
@ -32,17 +32,17 @@ Design Summary Report:
Number of LOCed External Input IBUFs 1 out of 1 100% Number of LOCed External Input IBUFs 1 out of 1 100%
Number of External Output IOBs 18 Number of External Output IOBs 19
Number of External Output IOBs 18 Number of External Output IOBs 19
Number of LOCed External Output IOBs 18 out of 18 100% Number of LOCed External Output IOBs 19 out of 19 100%
Number of External Bidir IOBs 0 Number of External Bidir IOBs 0
Number of BUFGMUXs 1 out of 24 4% Number of BUFGMUXs 2 out of 24 8%
Number of Slices 52 out of 2448 2% Number of Slices 318 out of 2448 12%
Number of SLICEMs 0 out of 1224 0% Number of SLICEMs 0 out of 1224 0%
@ -61,40 +61,43 @@ Total REAL time at the beginning of Placer: 1 secs
Total CPU time at the beginning of Placer: 1 secs Total CPU time at the beginning of Placer: 1 secs
Phase 1.1 Initial Placement Analysis Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:130c5420) REAL time: 1 secs Phase 1.1 Initial Placement Analysis (Checksum:6a29e20) REAL time: 1 secs
Phase 2.7 Design Feasibility Check Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:130c5420) REAL time: 1 secs Phase 2.7 Design Feasibility Check (Checksum:6a29e20) REAL time: 1 secs
Phase 3.31 Local Placement Optimization Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:130c5420) REAL time: 1 secs Phase 3.31 Local Placement Optimization (Checksum:6a29e20) REAL time: 1 secs
Phase 4.2 Initial Clock and IO Placement Phase 4.2 Initial Clock and IO Placement
Phase 4.2 Initial Clock and IO Placement (Checksum:2104b6b4) REAL time: 1 secs Phase 4.2 Initial Clock and IO Placement (Checksum:9fa8ca4e) REAL time: 2 secs
Phase 5.30 Global Clock Region Assignment Phase 5.30 Global Clock Region Assignment
Phase 5.30 Global Clock Region Assignment (Checksum:2104b6b4) REAL time: 1 secs Phase 5.30 Global Clock Region Assignment (Checksum:9fa8ca4e) REAL time: 2 secs
Phase 6.36 Local Placement Optimization Phase 6.36 Local Placement Optimization
Phase 6.36 Local Placement Optimization (Checksum:2104b6b4) REAL time: 1 secs Phase 6.36 Local Placement Optimization (Checksum:9fa8ca4e) REAL time: 2 secs
Phase 7.8 Global Placement Phase 7.8 Global Placement
......... ....................................
.. ..
Phase 7.8 Global Placement (Checksum:5dd09b6d) REAL time: 4 secs .............................................................................................
..
..
Phase 7.8 Global Placement (Checksum:672c9b54) REAL time: 5 secs
Phase 8.5 Local Placement Optimization Phase 8.5 Local Placement Optimization
Phase 8.5 Local Placement Optimization (Checksum:5dd09b6d) REAL time: 4 secs Phase 8.5 Local Placement Optimization (Checksum:672c9b54) REAL time: 5 secs
Phase 9.18 Placement Optimization Phase 9.18 Placement Optimization
Phase 9.18 Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs Phase 9.18 Placement Optimization (Checksum:482ffdf2) REAL time: 5 secs
Phase 10.5 Local Placement Optimization Phase 10.5 Local Placement Optimization
Phase 10.5 Local Placement Optimization (Checksum:4e40a4b4) REAL time: 4 secs Phase 10.5 Local Placement Optimization (Checksum:482ffdf2) REAL time: 5 secs
Total REAL time to Placer completion: 4 secs Total REAL time to Placer completion: 5 secs
Total CPU time to Placer completion: 4 secs Total CPU time to Placer completion: 5 secs
Writing design to file main.ncd Writing design to file main.ncd
@ -102,38 +105,34 @@ Writing design to file main.ncd
Starting Router Starting Router
Phase 1 : 319 unrouted; REAL time: 7 secs Phase 1 : 1798 unrouted; REAL time: 8 secs
Phase 2 : 284 unrouted; REAL time: 7 secs Phase 2 : 1669 unrouted; REAL time: 8 secs
Phase 3 : 35 unrouted; REAL time: 7 secs Phase 3 : 263 unrouted; REAL time: 8 secs
Phase 4 : 69 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 4 : 342 unrouted; (Par is working to improve performance) REAL time: 9 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs
Updating file: main.ncd with current fully routed design. Updating file: main.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 7 secs Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 9 secs Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 14 secs
Updating file: main.ncd with current fully routed design. Updating file: main.ncd with current fully routed design.
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 14 secs
Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs Phase 9 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs Phase 10 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs Phase 11 : 0 unrouted; (Par is working to improve performance) REAL time: 15 secs
Phase 12 : 0 unrouted; (Par is working to improve performance) REAL time: 10 secs Total REAL time to Router completion: 15 secs
WARNING:Route:455 - CLK Net:VGADriver/W may have excessive skew because Total CPU time to Router completion: 14 secs
2 CLK pins and 0 NON_CLK pins failed to route using a CLK template.
Total REAL time to Router completion: 10 secs
Total CPU time to Router completion: 9 secs
Partition Implementation Status Partition Implementation Status
------------------------------- -------------------------------
@ -151,9 +150,11 @@ Generating Clock Report
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)| | Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| CLK_BUFGP | BUFGMUX_X2Y1| No | 25 | 0.037 | 0.098 | | VGADriver/FRAME | BUFGMUX_X1Y10| No | 43 | 0.038 | 0.100 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
| VGADriver/W | Local| | 2 | 0.000 | 1.219 | | CLK_BUFGP | BUFGMUX_X2Y1| No | 39 | 0.038 | 0.101 |
+---------------------+--------------+------+------+------------+-------------+
| VGADriver/W | Local| | 1 | 0.000 | 1.110 |
+---------------------+--------------+------+------+------------+-------------+ +---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing * Net Skew is the difference between the minimum and maximum routing
@ -173,8 +174,11 @@ Asterisk (*) preceding a constraint indicates it was not met.
Constraint | Check | Worst Case | Best Case | Timing | Timing Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score | | Slack | Achievable | Errors | Score
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 5.493ns| N/A| 0 Autotimespec constraint for clock net VGA | SETUP | N/A| 11.237ns| N/A| 0
_BUFGP | HOLD | 1.410ns| | 0| 0 Driver/FRAME | HOLD | 0.850ns| | 0| 0
----------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net CLK | SETUP | N/A| 6.683ns| N/A| 0
_BUFGP | HOLD | 0.892ns| | 0| 0
---------------------------------------------------------------------------------------------------------- ----------------------------------------------------------------------------------------------------------
@ -190,16 +194,16 @@ Generating Pad Report.
All signals are completely routed. All signals are completely routed.
Total REAL time to PAR completion: 10 secs Total REAL time to PAR completion: 15 secs
Total CPU time to PAR completion: 9 secs Total CPU time to PAR completion: 15 secs
Peak Memory Usage: 228 MB Peak Memory Usage: 231 MB
Placement: Completed - No errors found. Placement: Completed - No errors found.
Routing: Completed - No errors found. Routing: Completed - No errors found.
Number of error messages: 0 Number of error messages: 0
Number of warning messages: 1 Number of warning messages: 0
Number of info messages: 1 Number of info messages: 1
Writing design to file main.ncd Writing design to file main.ncd

17
main.pcf
View file

@ -1,27 +1,28 @@
//! ************************************************************************** //! **************************************************************************
// Written by: Map P.15xf on Thu Feb 21 20:21:10 2013 // Written by: Map P.15xf on Fri Feb 22 15:42:11 2013
//! ************************************************************************** //! **************************************************************************
SCHEMATIC START; SCHEMATIC START;
COMP "HS" LOCATE = SITE "J14" LEVEL 1; COMP "HS" LOCATE = SITE "J14" LEVEL 1;
COMP "VS" LOCATE = SITE "K13" LEVEL 1;
COMP "CLK" LOCATE = SITE "M6" LEVEL 1;
COMP "POUT" LOCATE = SITE "B2" LEVEL 1;
COMP "LED<0>" LOCATE = SITE "M5" LEVEL 1; COMP "LED<0>" LOCATE = SITE "M5" LEVEL 1;
COMP "LED<1>" LOCATE = SITE "M11" LEVEL 1; COMP "LED<1>" LOCATE = SITE "M11" LEVEL 1;
COMP "LED<2>" LOCATE = SITE "P7" LEVEL 1; COMP "LED<2>" LOCATE = SITE "P7" LEVEL 1;
COMP "RGB<0>" LOCATE = SITE "H13" LEVEL 1;
COMP "LED<3>" LOCATE = SITE "P6" LEVEL 1; COMP "LED<3>" LOCATE = SITE "P6" LEVEL 1;
COMP "RGB<1>" LOCATE = SITE "J13" LEVEL 1;
COMP "LED<4>" LOCATE = SITE "N5" LEVEL 1; COMP "LED<4>" LOCATE = SITE "N5" LEVEL 1;
COMP "RGB<2>" LOCATE = SITE "F14" LEVEL 1;
COMP "LED<5>" LOCATE = SITE "N4" LEVEL 1; COMP "LED<5>" LOCATE = SITE "N4" LEVEL 1;
COMP "RGB<3>" LOCATE = SITE "G13" LEVEL 1;
COMP "LED<6>" LOCATE = SITE "P4" LEVEL 1; COMP "LED<6>" LOCATE = SITE "P4" LEVEL 1;
COMP "RGB<4>" LOCATE = SITE "G14" LEVEL 1;
COMP "LED<7>" LOCATE = SITE "G1" LEVEL 1; COMP "LED<7>" LOCATE = SITE "G1" LEVEL 1;
COMP "RGB<0>" LOCATE = SITE "H13" LEVEL 1;
COMP "RGB<1>" LOCATE = SITE "J13" LEVEL 1;
COMP "RGB<2>" LOCATE = SITE "F14" LEVEL 1;
COMP "RGB<3>" LOCATE = SITE "G13" LEVEL 1;
COMP "RGB<4>" LOCATE = SITE "G14" LEVEL 1;
COMP "RGB<5>" LOCATE = SITE "C14" LEVEL 1; COMP "RGB<5>" LOCATE = SITE "C14" LEVEL 1;
COMP "RGB<6>" LOCATE = SITE "D13" LEVEL 1; COMP "RGB<6>" LOCATE = SITE "D13" LEVEL 1;
COMP "VS" LOCATE = SITE "K13" LEVEL 1;
COMP "RGB<7>" LOCATE = SITE "F13" LEVEL 1; COMP "RGB<7>" LOCATE = SITE "F13" LEVEL 1;
COMP "CLK" LOCATE = SITE "M6" LEVEL 1;
NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT; NET "CLK_BUFGP/IBUFG" BEL "CLK_BUFGP/BUFG.GCLKMUX" USELOCALCONNECT;
SCHEMATIC END; SCHEMATIC END;

1
main.prj
View file

@ -1,2 +1,3 @@
vhdl work "vga.vhd" vhdl work "vga.vhd"
vhdl work "speaker.vhd"
vhdl work "main.vhd" vhdl work "main.vhd"

2
main.ptwx
View file

@ -329,4 +329,4 @@
<!ELEMENT twName (#PCDATA)> <!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)> <!ELEMENT twValue (#PCDATA)>
]> ]>
<twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK_BUFGP</twConstName><twConstData type="SETUP" best="5.493" units="ns" score="0"/><twConstData type="HOLD" slack="1.410" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="21">0</twUnmetConstCnt><twInfo anchorID="22">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport> <twReport><twBody><twSumRpt><twConstSummaryTable><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net VGADriver/FRAME</twConstName><twConstData type="SETUP" best="11.237" units="ns" score="0"/><twConstData type="HOLD" slack="0.850" units="ns" errors="0" score="0"/></twConstSummary><twConstSummary><twConstName UCFConstName="" ScopeName="">Autotimespec constraint for clock net CLK_BUFGP</twConstName><twConstData type="SETUP" best="6.683" units="ns" score="0"/><twConstData type="HOLD" slack="0.892" units="ns" errors="0" score="0"/></twConstSummary></twConstSummaryTable><twUnmetConstCnt anchorID="33">0</twUnmetConstCnt><twInfo anchorID="34">INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the constraint is not analyzed due to the following: No paths covered by this constraint; Other constraints intersect with this constraint; or This constraint was disabled by a Path Tracing Control. Please run the Timespec Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.</twInfo></twSumRpt></twBody></twReport>

471
main.syr
View file

@ -4,13 +4,13 @@ Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs Total CPU time to Xst completion: 0.12 secs
--> Parameter xsthdpdir set to xst --> Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs Total CPU time to Xst completion: 0.12 secs
--> Reading design: main.prj --> Reading design: main.prj
@ -104,17 +104,21 @@ Slice Utilization Ratio Delta : 5
========================================================================= =========================================================================
* HDL Compilation * * HDL Compilation *
========================================================================= =========================================================================
Compiling vhdl file "C:/fpga/pong/speaker.vhd" in Library work.
Architecture behavioral of Entity speaker is up to date.
Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work. Compiling vhdl file "C:/fpga/pong/vga.vhd" in Library work.
Entity <vga> compiled. Architecture behavioral of Entity vga is up to date.
Entity <vga> (Architecture <behavioral>) compiled.
Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work. Compiling vhdl file "C:/fpga/pong/main.vhd" in Library work.
Architecture behavioral of Entity main is up to date. Entity <main> compiled.
Entity <main> (Architecture <behavioral>) compiled.
========================================================================= =========================================================================
* Design Hierarchy Analysis * * Design Hierarchy Analysis *
========================================================================= =========================================================================
Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <main> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <speaker> in library <work> (architecture <behavioral>).
Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>). Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral>).
@ -122,10 +126,13 @@ Analyzing hierarchy for entity <vga> in library <work> (architecture <behavioral
* HDL Analysis * * HDL Analysis *
========================================================================= =========================================================================
Analyzing Entity <main> in library <work> (Architecture <behavioral>). Analyzing Entity <main> in library <work> (Architecture <behavioral>).
WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 57: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are: WARNING:Xst:819 - "C:/fpga/pong/main.vhd" line 85: One or more signals are missing in the process sensitivity list. To enable synthesis of FPGA/CPLD hardware, XST will assume that all necessary signals are present in the sensitivity list. Please note that the result of the synthesis may differ from the initial design specification. The missing signals are:
<w>, <x>, <y> <w>, <y>, <x>
Entity <main> analyzed. Unit <main> generated. Entity <main> analyzed. Unit <main> generated.
Analyzing Entity <speaker> in library <work> (Architecture <behavioral>).
Entity <speaker> analyzed. Unit <speaker> generated.
Analyzing Entity <vga> in library <work> (Architecture <behavioral>). Analyzing Entity <vga> in library <work> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated. Entity <vga> analyzed. Unit <vga> generated.
@ -136,32 +143,45 @@ Entity <vga> analyzed. Unit <vga> generated.
Performing bidirectional port resolution... Performing bidirectional port resolution...
Synthesizing Unit <speaker>.
Related source file is "C:/fpga/pong/speaker.vhd".
Found 25-bit register for signal <prescaler>.
Found 25-bit adder for signal <prescaler$add0000> created at line 33.
Found 1-bit register for signal <sout>.
Found 25-bit comparator greatequal for signal <sout$cmp_ge0000> created at line 29.
Summary:
inferred 26 D-type flip-flop(s).
inferred 1 Adder/Subtractor(s).
inferred 1 Comparator(s).
Unit <speaker> synthesized.
Synthesizing Unit <vga>. Synthesizing Unit <vga>.
Related source file is "C:/fpga/pong/vga.vhd". Related source file is "C:/fpga/pong/vga.vhd".
WARNING:Xst:1305 - Output <LED> is never assigned. Tied to value 00000000.
Found 1-bit register for signal <HS>. Found 1-bit register for signal <HS>.
Found 1-bit register for signal <W>. Found 1-bit register for signal <W>.
Found 10-bit register for signal <X>. Found 10-bit register for signal <X>.
Found 10-bit register for signal <Y>. Found 10-bit register for signal <Y>.
Found 1-bit register for signal <FRAME>.
Found 1-bit register for signal <VS>. Found 1-bit register for signal <VS>.
Found 8-bit register for signal <RGB>. Found 8-bit register for signal <RGB>.
Found 10-bit up counter for signal <horiz>. Found 10-bit up counter for signal <horiz>.
Found 11-bit comparator greater for signal <HS$cmp_gt0000> created at line 44. Found 11-bit comparator greater for signal <HS$cmp_gt0000> created at line 43.
Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 44. Found 11-bit comparator less for signal <HS$cmp_lt0000> created at line 43.
Found 10-bit up counter for signal <vert>. Found 10-bit up counter for signal <vert>.
Found 11-bit comparator greater for signal <VS$cmp_gt0000> created at line 50. Found 11-bit comparator greater for signal <VS$cmp_gt0000> created at line 49.
Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 50. Found 11-bit comparator less for signal <VS$cmp_lt0000> created at line 49.
Found 11-bit comparator greatequal for signal <W$cmp_ge0000> created at line 32. Found 11-bit comparator greatequal for signal <W$cmp_ge0000> created at line 32.
Found 11-bit comparator greatequal for signal <W$cmp_ge0001> created at line 32. Found 11-bit comparator greatequal for signal <W$cmp_ge0001> created at line 32.
Found 11-bit comparator less for signal <W$cmp_lt0000> created at line 32. Found 11-bit comparator less for signal <W$cmp_lt0000> created at line 32.
Found 11-bit comparator less for signal <W$cmp_lt0001> created at line 32. Found 11-bit comparator less for signal <W$cmp_lt0001> created at line 32.
Found 10-bit adder for signal <X$add0000> created at line 37. Found 10-bit adder for signal <X$add0000> created at line 36.
Found 10-bit subtractor for signal <X$addsub0000> created at line 37. Found 10-bit subtractor for signal <X$addsub0000> created at line 36.
Found 10-bit adder for signal <Y$add0000> created at line 38. Found 10-bit adder for signal <Y$add0000> created at line 37.
Found 10-bit subtractor for signal <Y$addsub0000> created at line 38. Found 10-bit subtractor for signal <Y$addsub0000> created at line 37.
Summary: Summary:
inferred 2 Counter(s). inferred 2 Counter(s).
inferred 31 D-type flip-flop(s). inferred 32 D-type flip-flop(s).
inferred 4 Adder/Subtractor(s). inferred 4 Adder/Subtractor(s).
inferred 8 Comparator(s). inferred 8 Comparator(s).
Unit <vga> synthesized. Unit <vga> synthesized.
@ -169,13 +189,92 @@ Unit <vga> synthesized.
Synthesizing Unit <main>. Synthesizing Unit <main>.
Related source file is "C:/fpga/pong/main.vhd". Related source file is "C:/fpga/pong/main.vhd".
WARNING:Xst:653 - Signal <ph> is used but never assigned. This sourceless signal will be automatically connected to value 00100000.
WARNING:Xst:653 - Signal <cw> is used but never assigned. This sourceless signal will be automatically connected to value 00001010.
WARNING:Xst:737 - Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems. WARNING:Xst:737 - Found 8-bit latch for signal <inrgb>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0000> created at line 59. Found 6-bit register for signal <cdx>.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0001> created at line 59. Found 6-bit adder for signal <cdx$addsub0000> created at line 129.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0000> created at line 59. Found 6-bit adder for signal <cdx$sub0000> created at line 105.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0001> created at line 59. Found 6-bit adder for signal <cdx$sub0001> created at line 121.
Found 6-bit register for signal <cdy>.
Found 6-bit adder for signal <cdy$sub0000> created at line 113.
Found 11-bit up accumulator for signal <cx>.
Found 11-bit up accumulator for signal <cy>.
Found 25-bit register for signal <hper>.
Found 11-bit adder for signal <hper$add0000> created at line 124.
Found 11-bit adder for signal <hper$add0001> created at line 116.
Found 11-bit subtractor for signal <hper$sub0000> created at line 124.
Found 11-bit subtractor for signal <hper$sub0001> created at line 116.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0000> created at line 161.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0001> created at line 161.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0002> created at line 162.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0003> created at line 162.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0004> created at line 164.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0005> created at line 164.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0006> created at line 166.
Found 11-bit comparator greatequal for signal <inrgb$cmp_ge0007> created at line 166.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0000> created at line 161.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0001> created at line 161.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0002> created at line 162.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0003> created at line 162.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0004> created at line 164.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0005> created at line 164.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0006> created at line 166.
Found 11-bit comparator lessequal for signal <inrgb$cmp_le0007> created at line 166.
Found 11-bit updown accumulator for signal <lp>.
Found 11-bit comparator greatequal for signal <lp$cmp_ge0000> created at line 134.
Found 6-bit comparator greatequal for signal <lp$cmp_ge0001> created at line 132.
Found 11-bit comparator greater for signal <lp$cmp_gt0000> created at line 133.
Found 11-bit comparator lessequal for signal <lp$cmp_le0000> created at line 133.
Found 11-bit subtractor for signal <lp$sub0000> created at line 134.
Found 19-bit register for signal <prescaler>.
Found 11-bit adder for signal <prescaler$add0000> created at line 124.
Found 11-bit adder for signal <prescaler$add0001> created at line 124.
Found 11-bit adder for signal <prescaler$add0002> created at line 116.
Found 11-bit adder for signal <prescaler$add0003> created at line 124.
Found 19-bit adder for signal <prescaler$addsub0000> created at line 151.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0000> created at line 124.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0001> created at line 124.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0002> created at line 116.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0003> created at line 116.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0004> created at line 108.
Found 11-bit comparator greatequal for signal <prescaler$cmp_ge0005> created at line 100.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0000> created at line 124.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0001> created at line 124.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0002> created at line 116.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0003> created at line 116.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0004> created at line 108.
Found 11-bit comparator lessequal for signal <prescaler$cmp_le0005> created at line 100.
Found 11-bit subtractor for signal <prescaler$sub0000> created at line 124.
Found 11-bit subtractor for signal <prescaler$sub0001> created at line 116.
Found 11-bit subtractor for signal <prescaler$sub0002> created at line 116.
Found 11-bit subtractor for signal <prescaler$sub0003> created at line 124.
Found 11-bit updown accumulator for signal <rp>.
Found 11-bit comparator greatequal for signal <rp$cmp_ge0000> created at line 140.
Found 11-bit comparator greater for signal <rp$cmp_gt0000> created at line 139.
Found 11-bit comparator lessequal for signal <rp$cmp_le0000> created at line 139.
Found 6-bit comparator less for signal <rp$cmp_lt0000> created at line 132.
Found 11-bit subtractor for signal <rp$sub0000> created at line 140.
Found 1-bit register for signal <son>.
Found 20-bit comparator greatequal for signal <son$cmp_ge0000> created at line 147.
Found 11-bit comparator greater for signal <son$cmp_gt0000> created at line 100.
Found 11-bit comparator greater for signal <son$cmp_gt0001> created at line 108.
Found 11-bit comparator greater for signal <son$cmp_gt0002> created at line 116.
Found 11-bit comparator greater for signal <son$cmp_gt0003> created at line 116.
Found 11-bit comparator greater for signal <son$cmp_gt0004> created at line 124.
Found 11-bit comparator greater for signal <son$cmp_gt0005> created at line 124.
Found 11-bit comparator less for signal <son$cmp_lt0000> created at line 100.
Found 11-bit comparator less for signal <son$cmp_lt0001> created at line 108.
Found 11-bit comparator less for signal <son$cmp_lt0002> created at line 116.
Found 11-bit comparator less for signal <son$cmp_lt0003> created at line 116.
Found 11-bit comparator less for signal <son$cmp_lt0004> created at line 124.
Found 11-bit comparator less for signal <son$cmp_lt0005> created at line 124.
Found 20-bit comparator less for signal <son$cmp_lt0006> created at line 147.
Summary: Summary:
inferred 4 Comparator(s). inferred 4 Accumulator(s).
inferred 57 D-type flip-flop(s).
inferred 19 Adder/Subtractor(s).
inferred 50 Comparator(s).
Unit <main> synthesized. Unit <main> synthesized.
@ -183,22 +282,38 @@ Unit <main> synthesized.
HDL Synthesis Report HDL Synthesis Report
Macro Statistics Macro Statistics
# Adders/Subtractors : 4 # Adders/Subtractors : 24
10-bit adder : 2 10-bit adder : 2
10-bit subtractor : 2 10-bit subtractor : 2
11-bit adder : 6
11-bit subtractor : 8
19-bit adder : 1
25-bit adder : 1
6-bit adder : 4
# Counters : 2 # Counters : 2
10-bit up counter : 2 10-bit up counter : 2
# Registers : 6 # Accumulators : 4
1-bit register : 3 11-bit up accumulator : 2
11-bit updown accumulator : 2
# Registers : 14
1-bit register : 6
10-bit register : 2 10-bit register : 2
19-bit register : 1
25-bit register : 2
6-bit register : 2
8-bit register : 1 8-bit register : 1
# Latches : 1 # Latches : 1
8-bit latch : 1 8-bit latch : 1
# Comparators : 12 # Comparators : 59
11-bit comparator greatequal : 4 11-bit comparator greatequal : 18
11-bit comparator greater : 2 11-bit comparator greater : 10
11-bit comparator less : 4 11-bit comparator less : 10
11-bit comparator lessequal : 2 11-bit comparator lessequal : 16
20-bit comparator greatequal : 1
20-bit comparator less : 1
25-bit comparator greatequal : 1
6-bit comparator greatequal : 1
6-bit comparator less : 1
========================================================================= =========================================================================
@ -206,43 +321,116 @@ Macro Statistics
* Advanced HDL Synthesis * * Advanced HDL Synthesis *
========================================================================= =========================================================================
WARNING:Xst:1293 - FF/Latch <hper_24> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_23> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_22> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_21> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_20> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_19> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_18> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_17> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_16> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_15> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_14> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_13> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_10> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_9> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_8> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_7> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_6> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_5> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_4> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_3> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_2> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
========================================================================= =========================================================================
Advanced HDL Synthesis Report Advanced HDL Synthesis Report
Macro Statistics Macro Statistics
# Adders/Subtractors : 4 # Adders/Subtractors : 24
10-bit adder : 2 10-bit adder : 2
10-bit subtractor : 2 10-bit subtractor : 2
11-bit adder : 6
11-bit subtractor : 8
19-bit adder : 1
25-bit adder : 1
6-bit adder : 4
# Counters : 2 # Counters : 2
10-bit up counter : 2 10-bit up counter : 2
# Registers : 31 # Accumulators : 4
Flip-Flops : 31 11-bit up accumulator : 2
11-bit updown accumulator : 2
# Registers : 115
Flip-Flops : 115
# Latches : 1 # Latches : 1
8-bit latch : 1 8-bit latch : 1
# Comparators : 12 # Comparators : 59
11-bit comparator greatequal : 4 11-bit comparator greatequal : 18
11-bit comparator greater : 2 11-bit comparator greater : 10
11-bit comparator less : 4 11-bit comparator less : 10
11-bit comparator lessequal : 2 11-bit comparator lessequal : 16
20-bit comparator greatequal : 1
20-bit comparator less : 1
25-bit comparator greatequal : 1
6-bit comparator greatequal : 1
6-bit comparator less : 1
========================================================================= =========================================================================
========================================================================= =========================================================================
* Low Level Synthesis * * Low Level Synthesis *
========================================================================= =========================================================================
INFO:Xst:2261 - The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 4 FFs/Latches, which will be removed : <6> <5> <1> <0> WARNING:Xst:1293 - FF/Latch <hper_24> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <4> in Unit <LPM_LATCH_1> is equivalent to the following 2 FFs/Latches, which will be removed : <3> <2> WARNING:Xst:1293 - FF/Latch <hper_23> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_22> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_21> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_20> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_19> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_18> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_17> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_16> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_15> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_14> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_13> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_10> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_9> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_8> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_7> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_6> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_5> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_4> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_3> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_2> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <hper_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
INFO:Xst:2261 - The FF/Latch <hper_11> in Unit <main> is equivalent to the following FF/Latch, which will be removed : <hper_12>
INFO:Xst:2261 - The FF/Latch <7> in Unit <LPM_LATCH_1> is equivalent to the following 7 FFs/Latches, which will be removed : <6> <5> <4> <3> <2> <1> <0>
WARNING:Xst:1293 - FF/Latch <cdy_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdy_1> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <main> ... Optimizing unit <main> ...
WARNING:Xst:1293 - FF/Latch <cdx_0> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_1> has a constant value of 0 in block <main>. This FF/Latch will be trimmed during the optimization process.
WARNING:Xst:1293 - FF/Latch <cdx_2> has a constant value of 1 in block <main>. This FF/Latch will be trimmed during the optimization process.
Optimizing unit <speaker> ...
Optimizing unit <vga> ... Optimizing unit <vga> ...
Mapping all equations... Mapping all equations...
Building and optimizing final netlist ... Building and optimizing final netlist ...
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_4> in Unit <main> is equivalent to the following 2 FFs/Latches, which will be removed : <VGADriver/RGB_3> <VGADriver/RGB_2> INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 7 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_4> <VGADriver/RGB_3> <VGADriver/RGB_2> <VGADriver/RGB_1> <VGADriver/RGB_0>
INFO:Xst:2261 - The FF/Latch <VGADriver/RGB_7> in Unit <main> is equivalent to the following 4 FFs/Latches, which will be removed : <VGADriver/RGB_6> <VGADriver/RGB_5> <VGADriver/RGB_1> <VGADriver/RGB_0> Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 13.
Found area constraint ratio of 100 (+ 5) on block main, actual ratio is 2. FlipFlop lp_5 has been replicated 1 time(s)
FlipFlop rp_5 has been replicated 1 time(s)
Final Macro Processing ... Final Macro Processing ...
@ -250,8 +438,8 @@ Final Macro Processing ...
Final Register Report Final Register Report
Macro Statistics Macro Statistics
# Registers : 45 # Registers : 145
Flip-Flops : 45 Flip-Flops : 145
========================================================================= =========================================================================
@ -277,35 +465,36 @@ Optimization Goal : Speed
Keep Hierarchy : No Keep Hierarchy : No
Design Statistics Design Statistics
# IOs : 19 # IOs : 20
Cell Usage : Cell Usage :
# BELS : 189 # BELS : 1250
# GND : 1 # GND : 1
# INV : 11 # INV : 71
# LUT1 : 33 # LUT1 : 76
# LUT2 : 1 # LUT2 : 225
# LUT2_L : 1 # LUT2_D : 2
# LUT3 : 6 # LUT2_L : 10
# LUT3 : 65
# LUT3_L : 3 # LUT3_L : 3
# LUT4 : 29 # LUT4 : 127
# LUT4_D : 1 # LUT4_D : 4
# LUT4_L : 4 # LUT4_L : 6
# MUXCY : 45 # MUXCY : 404
# MUXF5 : 3 # MUXF5 : 7
# VCC : 1 # VCC : 1
# XORCY : 50 # XORCY : 248
# FlipFlops/Latches : 47 # FlipFlops/Latches : 146
# FD : 1 # FD : 25
# FDE : 20 # FDE : 68
# FDR : 13 # FDR : 40
# FDRE : 10 # FDRE : 12
# FDS : 1 # LD : 1
# LD : 2 # Clock Buffers : 2
# Clock Buffers : 1 # BUFG : 1
# BUFGP : 1 # BUFGP : 1
# IO Buffers : 18 # IO Buffers : 19
# OBUF : 18 # OBUF : 19
========================================================================= =========================================================================
Device utilization summary: Device utilization summary:
@ -313,12 +502,12 @@ Device utilization summary:
Selected Device : 3s250ecp132-5 Selected Device : 3s250ecp132-5
Number of Slices: 50 out of 2448 2% Number of Slices: 314 out of 2448 12%
Number of Slice Flip Flops: 47 out of 4896 0% Number of Slice Flip Flops: 146 out of 4896 2%
Number of 4 input LUTs: 89 out of 4896 1% Number of 4 input LUTs: 589 out of 4896 12%
Number of IOs: 19 Number of IOs: 20
Number of bonded IOBs: 19 out of 92 20% Number of bonded IOBs: 20 out of 92 21%
Number of GCLKs: 1 out of 24 4% Number of GCLKs: 2 out of 24 8%
--------------------------- ---------------------------
Partition Resource Summary: Partition Resource Summary:
@ -341,8 +530,9 @@ Clock Information:
-----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load | Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+
VGADriver/W | NONE(inrgb_4) | 2 | VGADriver/FRAME1 | BUFG | 74 |
CLK | BUFGP | 45 | VGADriver/W | NONE(inrgb_7) | 1 |
CLK | BUFGP | 71 |
-----------------------------------+------------------------+-------+ -----------------------------------+------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems. INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.
@ -354,9 +544,9 @@ Timing Summary:
--------------- ---------------
Speed Grade: -5 Speed Grade: -5
Minimum period: 5.905ns (Maximum Frequency: 169.349MHz) Minimum period: 12.278ns (Maximum Frequency: 81.445MHz)
Minimum input arrival time before clock: No path found Minimum input arrival time before clock: No path found
Maximum output required time after clock: 4.221ns Maximum output required time after clock: 4.326ns
Maximum combinational path delay: No path found Maximum combinational path delay: No path found
Timing Detail: Timing Detail:
@ -364,35 +554,106 @@ Timing Detail:
All values displayed in nanoseconds (ns) All values displayed in nanoseconds (ns)
========================================================================= =========================================================================
Timing constraint: Default period analysis for Clock 'CLK' Timing constraint: Default period analysis for Clock 'VGADriver/FRAME1'
Clock period: 5.905ns (frequency: 169.349MHz) Clock period: 12.278ns (frequency: 81.445MHz)
Total number of paths / destination ports: 1505 / 95 Total number of paths / destination ports: 614702 / 124
------------------------------------------------------------------------- -------------------------------------------------------------------------
Delay: 5.905ns (Levels of Logic = 4) Delay: 12.278ns (Levels of Logic = 16)
Source: VGADriver/vert_6 (FF) Source: lp_6 (FF)
Destination: VGADriver/Y_9 (FF) Destination: son (FF)
Source Clock: CLK rising Source Clock: VGADriver/FRAME1 rising
Destination Clock: CLK rising Destination Clock: VGADriver/FRAME1 rising
Data Path: VGADriver/vert_6 to VGADriver/Y_9 Data Path: lp_6 to son
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FDRE:C->Q 4 0.514 0.651 VGADriver/vert_6 (VGADriver/vert_6) FDE:C->Q 19 0.514 0.925 lp_6 (lp_6)
LUT2_L:I0->LO 1 0.612 0.103 VGADriver/vert_cmp_eq00001_SW0 (VGADriver/X_and000093) LUT4:I3->O 5 0.612 0.607 hper_add0001<10>11 (hper_add0001<10>_bdd0)
LUT4:I3->O 3 0.612 0.454 VGADriver/vert_cmp_eq00001 (VGADriver/N7) LUT2:I1->O 1 0.612 0.000 hper_add0001<9>11 (hper_add0001<9>1)
LUT4_D:I3->O 4 0.612 0.502 VGADriver/X_and0000136 (VGADriver/X_and0000136) MUXCY:S->O 0 0.404 0.000 Madd_prescaler_add0002_cy<9> (Madd_prescaler_add0002_cy<9>)
LUT4:I3->O 10 0.612 0.750 VGADriver/X_and0000151_2 (VGADriver/X_and0000151_1) XORCY:CI->O 1 0.699 0.426 Madd_prescaler_add0002_xor<10> (prescaler_add0002<10>)
FDE:CE 0.483 VGADriver/Y_0 LUT2:I1->O 1 0.612 0.000 Mcompar_prescaler_cmp_le0003_lut<10> (Mcompar_prescaler_cmp_le0003_lut<10>)
MUXCY:S->O 3 0.752 0.454 Mcompar_prescaler_cmp_le0003_cy<10> (prescaler_cmp_le0003)
LUT4_D:I3->O 21 0.612 0.962 son_not0001557_1 (son_not0001557)
LUT4:I3->O 1 0.612 0.000 prescaler_mux0000<0>2 (prescaler_mux0000<0>)
MUXCY:S->O 1 0.404 0.000 Mcompar_son_cmp_lt0006_cy<0> (Mcompar_son_cmp_lt0006_cy<0>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<1> (Mcompar_son_cmp_lt0006_cy<1>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<2> (Mcompar_son_cmp_lt0006_cy<2>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<3> (Mcompar_son_cmp_lt0006_cy<3>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<4> (Mcompar_son_cmp_lt0006_cy<4>)
MUXCY:CI->O 1 0.052 0.000 Mcompar_son_cmp_lt0006_cy<5> (Mcompar_son_cmp_lt0006_cy<5>)
MUXCY:CI->O 21 0.399 0.962 Mcompar_son_cmp_lt0006_cy<6> (Mcompar_son_cmp_lt0006_cy<6>)
LUT4:I3->O 1 0.612 0.357 son_not000137 (son_not0001)
FDE:CE 0.483 son
---------------------------------------- ----------------------------------------
Total 5.905ns (3.445ns logic, 2.460ns route) Total 12.278ns (7.585ns logic, 4.693ns route)
(58.3% logic, 41.7% route) (61.8% logic, 38.2% route)
=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
Clock period: 7.122ns (frequency: 140.416MHz)
Total number of paths / destination ports: 10442 / 122
-------------------------------------------------------------------------
Delay: 7.122ns (Levels of Logic = 38)
Source: SpeakerDriver/prescaler_1 (FF)
Destination: SpeakerDriver/prescaler_24 (FF)
Source Clock: CLK rising
Destination Clock: CLK rising
Data Path: SpeakerDriver/prescaler_1 to SpeakerDriver/prescaler_24
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
FDR:C->Q 2 0.514 0.532 SpeakerDriver/prescaler_1 (SpeakerDriver/prescaler_1)
LUT1:I0->O 1 0.612 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>_rt (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>_rt)
MUXCY:S->O 1 0.404 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<0>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<1> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<1>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<2> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<2>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<3> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<3>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<4> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<4>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<5> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<5>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<6> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<6>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<7> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<7>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<8> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<8>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<9> (SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<9>)
MUXCY:CI->O 26 0.288 1.140 SpeakerDriver/Mcompar_sout_cmp_ge0000_cy<10> (SpeakerDriver/sout_cmp_ge0000)
LUT2:I1->O 1 0.612 0.000 SpeakerDriver/Madd_prescaler_add0000_lut<0> (SpeakerDriver/Madd_prescaler_add0000_lut<0>)
MUXCY:S->O 1 0.404 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<0> (SpeakerDriver/Madd_prescaler_add0000_cy<0>)
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<1> (SpeakerDriver/Madd_prescaler_add0000_cy<1>)
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<2> (SpeakerDriver/Madd_prescaler_add0000_cy<2>)
MUXCY:CI->O 1 0.052 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<3> (SpeakerDriver/Madd_prescaler_add0000_cy<3>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<4> (SpeakerDriver/Madd_prescaler_add0000_cy<4>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<5> (SpeakerDriver/Madd_prescaler_add0000_cy<5>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<6> (SpeakerDriver/Madd_prescaler_add0000_cy<6>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<7> (SpeakerDriver/Madd_prescaler_add0000_cy<7>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<8> (SpeakerDriver/Madd_prescaler_add0000_cy<8>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<9> (SpeakerDriver/Madd_prescaler_add0000_cy<9>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<10> (SpeakerDriver/Madd_prescaler_add0000_cy<10>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<11> (SpeakerDriver/Madd_prescaler_add0000_cy<11>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<12> (SpeakerDriver/Madd_prescaler_add0000_cy<12>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<13> (SpeakerDriver/Madd_prescaler_add0000_cy<13>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<14> (SpeakerDriver/Madd_prescaler_add0000_cy<14>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<15> (SpeakerDriver/Madd_prescaler_add0000_cy<15>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<16> (SpeakerDriver/Madd_prescaler_add0000_cy<16>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<17> (SpeakerDriver/Madd_prescaler_add0000_cy<17>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<18> (SpeakerDriver/Madd_prescaler_add0000_cy<18>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<19> (SpeakerDriver/Madd_prescaler_add0000_cy<19>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<20> (SpeakerDriver/Madd_prescaler_add0000_cy<20>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<21> (SpeakerDriver/Madd_prescaler_add0000_cy<21>)
MUXCY:CI->O 1 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<22> (SpeakerDriver/Madd_prescaler_add0000_cy<22>)
MUXCY:CI->O 0 0.051 0.000 SpeakerDriver/Madd_prescaler_add0000_cy<23> (SpeakerDriver/Madd_prescaler_add0000_cy<23>)
XORCY:CI->O 1 0.699 0.000 SpeakerDriver/Madd_prescaler_add0000_xor<24> (SpeakerDriver/prescaler_add0000<24>)
FDR:D 0.268 SpeakerDriver/prescaler_24
----------------------------------------
Total 7.122ns (5.449ns logic, 1.672ns route)
(76.5% logic, 23.5% route)
========================================================================= =========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK' Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
Total number of paths / destination ports: 10 / 10 Total number of paths / destination ports: 11 / 11
------------------------------------------------------------------------- -------------------------------------------------------------------------
Offset: 4.221ns (Levels of Logic = 1) Offset: 4.326ns (Levels of Logic = 1)
Source: VGADriver/RGB_7 (FF) Source: VGADriver/RGB_7 (FF)
Destination: RGB<7> (PAD) Destination: RGB<7> (PAD)
Source Clock: CLK rising Source Clock: CLK rising
@ -401,23 +662,23 @@ Offset: 4.221ns (Levels of Logic = 1)
Gate Net Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name) Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------ ---------------------------------------- ------------
FDS:C->Q 5 0.514 0.538 VGADriver/RGB_7 (VGADriver/RGB_7) FDR:C->Q 8 0.514 0.643 VGADriver/RGB_7 (VGADriver/RGB_7)
OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>) OBUF:I->O 3.169 RGB_0_OBUF (RGB<0>)
---------------------------------------- ----------------------------------------
Total 4.221ns (3.683ns logic, 0.538ns route) Total 4.326ns (3.683ns logic, 0.643ns route)
(87.3% logic, 12.7% route) (85.1% logic, 14.9% route)
========================================================================= =========================================================================
Total REAL time to Xst completion: 6.00 secs Total REAL time to Xst completion: 10.00 secs
Total CPU time to Xst completion: 5.42 secs Total CPU time to Xst completion: 9.75 secs
--> -->
Total memory usage is 217424 kilobytes Total memory usage is 225232 kilobytes
Number of errors : 0 ( 0 filtered) Number of errors : 0 ( 0 filtered)
Number of warnings : 3 ( 0 filtered) Number of warnings : 61 ( 0 filtered)
Number of infos : 5 ( 0 filtered) Number of infos : 4 ( 0 filtered)

27
main.twr
View file

@ -44,16 +44,17 @@ Clock CLK to Pad
| clk (edge) | | Clock | | clk (edge) | | Clock |
Destination | to PAD |Internal Clock(s) | Phase | Destination | to PAD |Internal Clock(s) | Phase |
------------+------------+------------------+--------+ ------------+------------+------------------+--------+
HS | 6.320(R)|CLK_BUFGP | 0.000| HS | 6.322(R)|CLK_BUFGP | 0.000|
RGB<0> | 7.061(R)|CLK_BUFGP | 0.000| POUT | 8.112(R)|CLK_BUFGP | 0.000|
RGB<1> | 7.052(R)|CLK_BUFGP | 0.000| RGB<0> | 6.754(R)|CLK_BUFGP | 0.000|
RGB<2> | 7.348(R)|CLK_BUFGP | 0.000| RGB<1> | 6.745(R)|CLK_BUFGP | 0.000|
RGB<3> | 7.565(R)|CLK_BUFGP | 0.000| RGB<2> | 7.196(R)|CLK_BUFGP | 0.000|
RGB<4> | 7.538(R)|CLK_BUFGP | 0.000| RGB<3> | 7.322(R)|CLK_BUFGP | 0.000|
RGB<5> | 8.606(R)|CLK_BUFGP | 0.000| RGB<4> | 6.975(R)|CLK_BUFGP | 0.000|
RGB<6> | 8.389(R)|CLK_BUFGP | 0.000| RGB<5> | 8.297(R)|CLK_BUFGP | 0.000|
RGB<7> | 7.981(R)|CLK_BUFGP | 0.000| RGB<6> | 8.081(R)|CLK_BUFGP | 0.000|
VS | 6.627(R)|CLK_BUFGP | 0.000| RGB<7> | 7.578(R)|CLK_BUFGP | 0.000|
VS | 6.132(R)|CLK_BUFGP | 0.000|
------------+------------+------------------+--------+ ------------+------------+------------------+--------+
Clock to Setup on destination clock CLK Clock to Setup on destination clock CLK
@ -61,18 +62,18 @@ Clock to Setup on destination clock CLK
| Src:Rise| Src:Fall| Src:Rise| Src:Fall| | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
CLK | 5.493| | | | CLK | 6.683| | | |
---------------+---------+---------+---------+---------+ ---------------+---------+---------+---------+---------+
Analysis completed Thu Feb 21 20:21:26 2013 Analysis completed Fri Feb 22 15:42:34 2013
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
Trace Settings: Trace Settings:
------------------------- -------------------------
Trace Settings Trace Settings
Peak Memory Usage: 129 MB Peak Memory Usage: 134 MB

4
main.twx
View file

@ -332,7 +332,7 @@
<twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n <twReport><twHead anchorID="1"><twExecVer>Release 14.1 Trace (nt)</twExecVer><twCopyright>Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>C:\Xilinx\14.1\ISE_DS\ISE\bin\nt\unwrapped\trce.exe -intstyle ise -v 3 -s 5 -n
3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf 3 -fastpaths -xml main.twx main.ncd -o main.twr main.pcf -ucf pins.ucf
</twCmdLine><twDesign>main.ncd</twDesign><twDesignPath>main.ncd</twDesignPath><twPCF>main.pcf</twPCF><twPcfPath>main.pcf</twPcfPath><twDevInfo arch="spartan3e" pkg="cp132"><twDevName>xc3s250e</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2012-04-23</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="6">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="7">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="8" twNameLen="15"><twClk2OutList anchorID="9" twDestWidth="6" twPhaseWidth="9"><twSrc>CLK</twSrc><twClk2Out twOutPad = "HS" twMinTime = "5.125" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.320" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;0&gt;" twMinTime = "5.717" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.061" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;1&gt;" twMinTime = "5.710" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.052" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;2&gt;" twMinTime = "5.948" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.348" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;3&gt;" twMinTime = "6.121" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.565" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;4&gt;" twMinTime = "6.100" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.538" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;5&gt;" twMinTime = "6.953" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.606" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;6&gt;" twMinTime = "6.780" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.389" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;7&gt;" twMinTime = "6.453" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.981" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "VS" twMinTime = "5.372" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.627" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="10" twDestWidth="3"><twDest>CLK</twDest><twClk2SU><twSrc>CLK</twSrc><twRiseRise>5.493</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Thu Feb 21 20:21:26 2013 </twTimestamp></twFoot><twClientInfo anchorID="11"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue> </twCmdLine><twDesign>main.ncd</twDesign><twDesignPath>main.ncd</twDesignPath><twPCF>main.pcf</twPCF><twPcfPath>main.pcf</twPcfPath><twDevInfo arch="spartan3e" pkg="cp132"><twDevName>xc3s250e</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.27 2012-04-23</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="6">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="7">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="8" twNameLen="15"><twClk2OutList anchorID="9" twDestWidth="6" twPhaseWidth="9"><twSrc>CLK</twSrc><twClk2Out twOutPad = "HS" twMinTime = "5.127" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.322" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "POUT" twMinTime = "6.625" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.112" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;0&gt;" twMinTime = "5.472" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.754" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;1&gt;" twMinTime = "5.465" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.745" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;2&gt;" twMinTime = "5.826" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.196" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;3&gt;" twMinTime = "5.927" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.322" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;4&gt;" twMinTime = "5.649" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.975" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;5&gt;" twMinTime = "6.707" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.297" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;6&gt;" twMinTime = "6.534" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "8.081" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "RGB&lt;7&gt;" twMinTime = "6.131" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "7.578" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out><twClk2Out twOutPad = "VS" twMinTime = "4.975" twMinCrnr="f" twMinEdge ="twRising" twMaxTime = "6.132" twMaxCrnr="f" twMaxEdge ="twRising" twInternalClk="CLK_BUFGP" twClkPhase="0.000" ></twClk2Out></twClk2OutList><twClk2SUList anchorID="10" twDestWidth="3"><twDest>CLK</twDest><twClk2SU><twSrc>CLK</twSrc><twRiseRise>6.683</twRiseRise></twClk2SU></twClk2SUList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Fri Feb 22 15:42:34 2013 </twTimestamp></twFoot><twClientInfo anchorID="11"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 129 MB Peak Memory Usage: 134 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport> </twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

2
main.unroutes
View file

@ -1,7 +1,7 @@
Release 14.1 - par P.15xf (nt) Release 14.1 - par P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Thu Feb 21 20:21:23 2013 Fri Feb 22 15:42:30 2013
All signals are completely routed. All signals are completely routed.

126
main.vhd
View file

@ -8,6 +8,9 @@ entity main is
CLK : in std_logic; CLK : in std_logic;
LED : out std_logic_vector(7 downto 0); LED : out std_logic_vector(7 downto 0);
POUT : out std_logic;
RGB : out std_logic_vector(7 downto 0); RGB : out std_logic_vector(7 downto 0);
HS : out std_logic; HS : out std_logic;
@ -20,12 +23,11 @@ architecture Behavioral of main is
port ( port (
CLK : in std_logic; CLK : in std_logic;
LED : out std_logic_vector(7 downto 0);
IRGB : in std_logic_vector(7 downto 0); IRGB : in std_logic_vector(7 downto 0);
RGB : out std_logic_vector(7 downto 0); RGB : out std_logic_vector(7 downto 0);
FRAME : out std_logic;
W : out std_logic; W : out std_logic;
X : out std_logic_vector(9 downto 0); X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(9 downto 0); Y : out std_logic_vector(9 downto 0);
@ -35,31 +37,137 @@ architecture Behavioral of main is
); );
end component; end component;
component speaker is
port (
CLK: in std_logic;
HPERIOD: in std_logic_vector(24 downto 0);
PLAY: in std_logic;
PIN: out std_logic
);
end component;
signal son : std_logic := '0';
signal hper : std_logic_vector(24 downto 0) := "0000000000110000000010010";
signal inrgb : std_logic_vector(7 downto 0) := "00000000"; signal inrgb : std_logic_vector(7 downto 0) := "00000000";
signal fclk : std_logic;
signal w : std_logic; signal w : std_logic;
signal x : std_logic_vector(9 downto 0); signal x : std_logic_vector(9 downto 0);
signal y : std_logic_vector(9 downto 0); signal y : std_logic_vector(9 downto 0);
begin begin
LED <= "00000000";
SpeakerDriver : component speaker port map (
CLK => CLK,
HPERIOD => hper,
PLAY => son,
PIN => POUT
);
VGADriver : component vga port map ( VGADriver : component vga port map (
CLK => CLK, CLK => CLK,
LED => LED,
HS => HS, HS => HS,
VS => VS, VS => VS,
RGB => RGB, RGB => RGB,
IRGB => inrgb, IRGB => inrgb,
FRAME => fclk,
W => w, W => w,
X => x, X => x,
Y => y Y => y
); );
process (CLK) begin process (CLK, fclk)
if w = '1' then variable prescaler : std_logic_vector(18 downto 0) := (others => '0');
if x >= 300 and x <= 340 and y >= 220 and y <= 260 then
inrgb <= "11100011"; variable ph : signed(7 downto 0) := "00100000";
variable lp : signed(10 downto 0) := "00011110000";
variable rp : signed(10 downto 0) := "00011110000";
variable cx : signed(10 downto 0) := "00101000000";
variable cdx : signed(5 downto 0) := "000100";
variable cy : signed(10 downto 0) := "00011110000";
variable cdy : signed(5 downto 0) := "000010";
variable cw : signed(7 downto 0) := "00001010";
begin
-- called at 60 Hz, handle game logic here
if fclk'event and fclk = '1' then
if cx-cw <= 0 or cx+cw >= 640 then
prescaler := (others => '0');
son <= '1';
hper <= "0000000000111100000010010";
cdx := -cdx;
end if;
if cy-cw <= 25 or cy+cw >= 455 then
prescaler := (others => '0');
son <= '1';
hper <= "0000000000111100000010010";
cdy := -cdy;
end if;
if cx-cw >= 50 and cx-cw <= 60 and (cy-cw >= lp-ph-cw and cy+cw <= lp+ph+cw) then
prescaler := (others => '0');
son <= '1';
hper <= "0000000000110000000010010";
cdx := -cdx;
end if;
if cx+cw >= 580 and cx+cw <= 590 and (cy-cw >= rp-ph-cw and cy+cw <= rp+ph+cw) then
prescaler := (others => '0');
son <= '1';
hper <= "0000000000110000000010010";
cdx := -cdx;
end if;
if cdx < 0 then
if lp-cy > 0 then
lp := lp-4;
elsif lp-cy < 0 then
lp := lp+4;
end if;
else else
inrgb <= "00011100"; if rp-cy > 0 then
rp := rp-4;
elsif rp-cy < 0 then
rp := rp+4;
end if;
end if;
if son = '1' then
if prescaler >= 5 then
son <= '0';
prescaler := (others => '0');
else
prescaler := prescaler + 1;
end if;
end if;
cx := cx + cdx;
cy := cy + cdy;
end if;
-- called whenver drawing, handle graphic logic here
if w = '1' then
if (y >= 10 and y <= 20) or (y <= 470 and y >= 460) then
inrgb <= "11111111";
elsif x >= 45 and x <= 60 and y >= lp-ph and y <= lp+ph then
inrgb <= "11111111";
elsif x >= 580 and x <= 595 and y >= rp-ph and y <= rp+ph then
inrgb <= "11111111";
elsif x >= cx-cw and x <= cx+cw and y >= cy-cw and y <= cy+cw then
inrgb <= "11111111";
else
inrgb <= "00000000";
end if; end if;
end if; end if;
end process; end process;

2
main_guide.ncd
View file

File diff suppressed because one or more lines are too long

34
main_map.map
View file

@ -9,7 +9,7 @@ Target Device : xc3s250e
Target Package : cp132 Target Package : cp132
Target Speed : -5 Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.55 $ Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Thu Feb 21 20:21:08 2013 Mapped Date : Fri Feb 22 15:42:09 2013
Mapping design into LUTs... Mapping design into LUTs...
Running directed packing... Running directed packing...
@ -24,30 +24,30 @@ Design Summary:
Number of errors: 0 Number of errors: 0
Number of warnings: 0 Number of warnings: 0
Logic Utilization: Logic Utilization:
Total Number Slice Registers: 47 out of 4,896 1% Total Number Slice Registers: 146 out of 4,896 2%
Number used as Flip Flops: 45 Number used as Flip Flops: 145
Number used as Latches: 2 Number used as Latches: 1
Number of 4 input LUTs: 58 out of 4,896 1% Number of 4 input LUTs: 508 out of 4,896 10%
Logic Distribution: Logic Distribution:
Number of occupied Slices: 52 out of 2,448 2% Number of occupied Slices: 318 out of 2,448 12%
Number of Slices containing only related logic: 52 out of 52 100% Number of Slices containing only related logic: 318 out of 318 100%
Number of Slices containing unrelated logic: 0 out of 52 0% Number of Slices containing unrelated logic: 0 out of 318 0%
*See NOTES below for an explanation of the effects of unrelated logic. *See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 92 out of 4,896 1% Total Number of 4 input LUTs: 584 out of 4,896 11%
Number used as logic: 58 Number used as logic: 508
Number used as a route-thru: 34 Number used as a route-thru: 76
The Slice Logic Distribution report is not meaningful if the design is The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 19 out of 92 20% Number of bonded IOBs: 20 out of 92 21%
Number of BUFGMUXs: 1 out of 24 4% Number of BUFGMUXs: 2 out of 24 8%
Average Fanout of Non-Clock Nets: 2.67 Average Fanout of Non-Clock Nets: 2.78
Peak Memory Usage: 209 MB Peak Memory Usage: 212 MB
Total REAL time to MAP completion: 1 secs Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 1 secs Total CPU time to MAP completion: 2 secs
NOTES: NOTES:

39
main_map.mrp
View file

@ -9,37 +9,37 @@ Target Device : xc3s250e
Target Package : cp132 Target Package : cp132
Target Speed : -5 Target Speed : -5
Mapper Version : spartan3e -- $Revision: 1.55 $ Mapper Version : spartan3e -- $Revision: 1.55 $
Mapped Date : Thu Feb 21 20:21:08 2013 Mapped Date : Fri Feb 22 15:42:09 2013
Design Summary Design Summary
-------------- --------------
Number of errors: 0 Number of errors: 0
Number of warnings: 0 Number of warnings: 0
Logic Utilization: Logic Utilization:
Total Number Slice Registers: 47 out of 4,896 1% Total Number Slice Registers: 146 out of 4,896 2%
Number used as Flip Flops: 45 Number used as Flip Flops: 145
Number used as Latches: 2 Number used as Latches: 1
Number of 4 input LUTs: 58 out of 4,896 1% Number of 4 input LUTs: 508 out of 4,896 10%
Logic Distribution: Logic Distribution:
Number of occupied Slices: 52 out of 2,448 2% Number of occupied Slices: 318 out of 2,448 12%
Number of Slices containing only related logic: 52 out of 52 100% Number of Slices containing only related logic: 318 out of 318 100%
Number of Slices containing unrelated logic: 0 out of 52 0% Number of Slices containing unrelated logic: 0 out of 318 0%
*See NOTES below for an explanation of the effects of unrelated logic. *See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 92 out of 4,896 1% Total Number of 4 input LUTs: 584 out of 4,896 11%
Number used as logic: 58 Number used as logic: 508
Number used as a route-thru: 34 Number used as a route-thru: 76
The Slice Logic Distribution report is not meaningful if the design is The Slice Logic Distribution report is not meaningful if the design is
over-mapped for a non-slice resource or if Placement fails. over-mapped for a non-slice resource or if Placement fails.
Number of bonded IOBs: 19 out of 92 20% Number of bonded IOBs: 20 out of 92 21%
Number of BUFGMUXs: 1 out of 24 4% Number of BUFGMUXs: 2 out of 24 8%
Average Fanout of Non-Clock Nets: 2.67 Average Fanout of Non-Clock Nets: 2.78
Peak Memory Usage: 209 MB Peak Memory Usage: 212 MB
Total REAL time to MAP completion: 1 secs Total REAL time to MAP completion: 2 secs
Total CPU time to MAP completion: 1 secs Total CPU time to MAP completion: 2 secs
NOTES: NOTES:
@ -87,7 +87,7 @@ INFO:MapLib:562 - No environment variables are currently set.
Section 4 - Removed Logic Summary Section 4 - Removed Logic Summary
--------------------------------- ---------------------------------
2 block(s) optimized away 4 block(s) optimized away
Section 5 - Removed Logic Section 5 - Removed Logic
------------------------- -------------------------
@ -96,6 +96,8 @@ Optimized Block(s):
TYPE BLOCK TYPE BLOCK
GND XST_GND GND XST_GND
VCC XST_VCC VCC XST_VCC
MUXCY Maccum_cx_cy<0>
MUXCY Maccum_cy_cy<0>
To enable printing of redundant blocks removed and signals merged, set the To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map. detailed map report option and rerun map.
@ -117,6 +119,7 @@ Section 6 - IOB Properties
| LED<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | LED<5> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| LED<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | LED<6> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| LED<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 | | LED<7> | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| POUT | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | 0 / 0 |
| RGB<0> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | | RGB<0> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
| RGB<1> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | | RGB<1> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |
| RGB<2> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 | | RGB<2> | IOB | OUTPUT | LVCMOS33 | | 8 | FAST | | | 0 / 0 |

2
main_map.ncd
View file

File diff suppressed because one or more lines are too long

2
main_map.ngm
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File diff suppressed because one or more lines are too long

51
main_map.xrpt
View file

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Map" timeStamp="Thu Feb 21 20:21:10 2013"> <application stringID="Map" timeStamp="Fri Feb 22 15:42:12 2013">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@ -73,29 +73,29 @@
<item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/> <item dataType="int" stringID="MAP_NUM_ERRORS" value="0"/>
<item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_FILTERED_WARNINGS" value="0"/>
<item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/> <item dataType="int" stringID="MAP_NUM_WARNINGS" value="0"/>
<item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="214240"/> <item UNITS="KB" dataType="int" stringID="MAP_PEAK_MEMORY" value="217248"/>
<item stringID="MAP_TOTAL_REAL_TIME" value="1 secs "/> <item stringID="MAP_TOTAL_REAL_TIME" value="2 secs "/>
<item stringID="MAP_TOTAL_CPU_TIME" value="1 secs "/> <item stringID="MAP_TOTAL_CPU_TIME" value="2 secs "/>
</section> </section>
<section stringID="MAP_SLICE_REPORTING"> <section stringID="MAP_SLICE_REPORTING">
<item AVAILABLE="4896" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="47"> <item AVAILABLE="4896" dataType="int" label="Number of Slice Registers" stringID="MAP_SLICE_REGISTERS" value="146">
<item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="45"/> <item dataType="int" label="Number of Slice Flip Flops" stringID="MAP_NUM_SLICE_FF" value="145"/>
<item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="2"/> <item dataType="int" stringID="MAP_NUM_SLICE_LATCH" value="1"/>
</item> </item>
<item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="92"> <item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="MAP_NUM_4_INPUT_LUT" value="584">
<item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="34"/> <item dataType="int" label="Number of route-thrus" stringID="MAP_NUM_LUT_RT" value="76"/>
</item> </item>
<item AVAILABLE="2448" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="52"> <item AVAILABLE="2448" dataType="int" label="Number of occupied Slices" stringID="MAP_OCCUPIED_SLICES" value="318">
<item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/> <item dataType="int" label="Number of Slices containing unrelated logic" stringID="MAP_NUM_SLICE_UNRELATED" value="0"/>
</item> </item>
</section> </section>
<section stringID="MAP_IOB_REPORTING"> <section stringID="MAP_IOB_REPORTING">
<section stringID="MAP_IOB_DATA"> <section stringID="MAP_IOB_DATA">
<item AVAILABLE="92" dataType="int" stringID="MAP_AGG_BONDED_IO" value="19"/> <item AVAILABLE="92" dataType="int" stringID="MAP_AGG_BONDED_IO" value="20"/>
</section> </section>
</section> </section>
<section stringID="MAP_HARD_IP_REPORTING"> <section stringID="MAP_HARD_IP_REPORTING">
<item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="1"/> <item AVAILABLE="24" dataType="int" label="Number of BUFGMUXs" stringID="MAP_NUM_BUFGMUX" value="2"/>
</section> </section>
<section stringID="MAP_MACRO_RPM_REPORTING"> <section stringID="MAP_MACRO_RPM_REPORTING">
<item dataType="int" stringID="MAP_HARD_MACROS" value="0"/> <item dataType="int" stringID="MAP_HARD_MACROS" value="0"/>
@ -202,6 +202,15 @@
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="11"> <row stringID="row" value="11">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="POUT"/>
<item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_STANDARD" value="LVCMOS25"/>
<item label="Drive&#xA;Strength" stringID="DRIVE_STRENGTH" value="12"/>
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="SLOW"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row>
<row stringID="row" value="12">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;0>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;0>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -210,7 +219,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="12"> <row stringID="row" value="13">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;1>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;1>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -219,7 +228,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="13"> <row stringID="row" value="14">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;2>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;2>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -228,7 +237,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="14"> <row stringID="row" value="15">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;3>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;3>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -237,7 +246,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="15"> <row stringID="row" value="16">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;4>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;4>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -246,7 +255,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="16"> <row stringID="row" value="17">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;5>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;5>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -255,7 +264,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="17"> <row stringID="row" value="18">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;6>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;6>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -264,7 +273,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="18"> <row stringID="row" value="19">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;7>"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="RGB&lt;7>"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -273,7 +282,7 @@
<item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/> <item label="Slew&#xA;Rate" stringID="SLEW_RATE" value="FAST"/>
<item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/> <item label="IOB&#xA;Delay" stringID="IOB_DELAY" value="0 / 0"/>
</row> </row>
<row stringID="row" value="19"> <row stringID="row" value="20">
<item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VS"/> <item label="IOB&#xA;Name" sort="smart" stringID="IOB_NAME" value="VS"/>
<item stringID="Type" value="IOB"/> <item stringID="Type" value="IOB"/>
<item stringID="Direction" value="OUTPUT"/> <item stringID="Direction" value="OUTPUT"/>
@ -286,7 +295,7 @@
</section> </section>
<section stringID="MAP_RPM_MACROS"> <section stringID="MAP_RPM_MACROS">
<section stringID="MAP_SHAPE_SECTION"> <section stringID="MAP_SHAPE_SECTION">
<item dataType="int" stringID="MAP_NUM_SHAPE" value="5"/> <item dataType="int" stringID="MAP_NUM_SHAPE" value="40"/>
</section> </section>
</section> </section>
<section stringID="MAP_GUIDE_REPORT"/> <section stringID="MAP_GUIDE_REPORT"/>

77
main_ngdbuild.xrpt
View file

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="NgdBuild" timeStamp="Thu Feb 21 20:21:06 2013"> <application stringID="NgdBuild" timeStamp="Fri Feb 22 15:42:07 2013">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@ -70,53 +70,54 @@
<item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/> <item dataType="int" stringID="NGDBUILD_NUM_INFOS" value="0"/>
</section> </section>
<section stringID="NGDBUILD_PRE_UNISIM_SUMMARY"> <section stringID="NGDBUILD_PRE_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFGP" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="20"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="68"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="13"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="10"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="71"/>
<item dataType="int" stringID="NGDBUILD_NUM_LD" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LD" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="76"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2_D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="29"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="127"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="45"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="50"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="248"/>
</section> </section>
<section stringID="NGDBUILD_POST_UNISIM_SUMMARY"> <section stringID="NGDBUILD_POST_UNISIM_SUMMARY">
<item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_BUFG" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_FD" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_FD" value="25"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDE" value="20"/> <item dataType="int" stringID="NGDBUILD_NUM_FDE" value="68"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDR" value="13"/> <item dataType="int" stringID="NGDBUILD_NUM_FDR" value="40"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="10"/> <item dataType="int" stringID="NGDBUILD_NUM_FDRE" value="12"/>
<item dataType="int" stringID="NGDBUILD_NUM_FDS" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_GND" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_IBUFG" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_INV" value="11"/> <item dataType="int" stringID="NGDBUILD_NUM_INV" value="71"/>
<item dataType="int" stringID="NGDBUILD_NUM_LD" value="2"/> <item dataType="int" stringID="NGDBUILD_NUM_LD" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="33"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT1" value="76"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2" value="225"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2_D" value="2"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="6"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT2_L" value="10"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3" value="65"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT3_L" value="3"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="29"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4" value="127"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4_D" value="4"/>
<item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="4"/> <item dataType="int" stringID="NGDBUILD_NUM_LUT4_L" value="6"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="45"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXCY" value="404"/>
<item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="3"/> <item dataType="int" stringID="NGDBUILD_NUM_MUXF5" value="7"/>
<item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="18"/> <item dataType="int" stringID="NGDBUILD_NUM_OBUF" value="19"/>
<item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/> <item dataType="int" stringID="NGDBUILD_NUM_VCC" value="1"/>
<item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="50"/> <item dataType="int" stringID="NGDBUILD_NUM_XORCY" value="248"/>
</section> </section>
<section stringID="NGDBUILD_CORE_GENERATION_SUMMARY"> <section stringID="NGDBUILD_CORE_GENERATION_SUMMARY">
<section stringID="NGDBUILD_CORE_INSTANCES"/> <section stringID="NGDBUILD_CORE_INSTANCES"/>

4
main_pad.csv
View file

@ -1,7 +1,7 @@
#Release 14.1 - par P.15xf (nt) #Release 14.1 - par P.15xf (nt)
#Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. #Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
#Thu Feb 21 20:21:23 2013 #Fri Feb 22 15:42:30 2013
# #
## NOTE: This file is designed to be imported into a spreadsheet program ## NOTE: This file is designed to be imported into a spreadsheet program
@ -34,7 +34,7 @@ A12,,DIFFS,IO_L02N_0,UNUSED,,0,,,,,,,,,
A13,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,, A13,,DIFFM,IO_L01P_0,UNUSED,,0,,,,,,,,,
A14,,,TDO,,,,,,,,,,,, A14,,,TDO,,,,,,,,,,,,
B1,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,, B1,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,,
B2,,DIFFM,IO_L01P_3,UNUSED,,3,,,,,,,,, B2,POUT,IOB,IO_L01P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
B3,,DIFFS,IO_L11N_0/HSWAP,UNUSED,,0,,,,,,,,, B3,,DIFFS,IO_L11N_0/HSWAP,UNUSED,,0,,,,,,,,,
B4,,DIFFM,IO_L10P_0,UNUSED,,0,,,,,,,,, B4,,DIFFM,IO_L10P_0,UNUSED,,0,,,,,,,,,
B5,,DIFFM,IO_L09P_0,UNUSED,,0,,,,,,,,, B5,,DIFFM,IO_L09P_0,UNUSED,,0,,,,,,,,,

1 #Release 14.1 - par P.15xf (nt)
2 #Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
3 #Thu Feb 21 20:21:23 2013 #Fri Feb 22 15:42:30 2013
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
34 B1,,DIFFS,IO_L01N_3,UNUSED,,3,,,,,,,,,
35 B2,,DIFFM,IO_L01P_3,UNUSED,,3,,,,,,,,, B2,POUT,IOB,IO_L01P_3,OUTPUT,LVCMOS25*,3,12,SLOW,NONE**,,,LOCATED,NO,NONE,
36 B3,,DIFFS,IO_L11N_0/HSWAP,UNUSED,,0,,,,,,,,,
37 B4,,DIFFM,IO_L10P_0,UNUSED,,0,,,,,,,,,
38 B5,,DIFFM,IO_L09P_0,UNUSED,,0,,,,,,,,,
39 B6,,DIFFM,IO_L08P_0,UNUSED,,0,,,,,,,,,
40 B7,,DIFFS,IO_L07N_0/GCLK11,UNUSED,,0,,,,,,,,,

4
main_pad.txt
View file

@ -1,7 +1,7 @@
Release 14.1 - par P.15xf (nt) Release 14.1 - par P.15xf (nt)
Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved. Copyright (c) 1995-2012 Xilinx, Inc. All rights reserved.
Thu Feb 21 20:21:23 2013 Fri Feb 22 15:42:30 2013
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
@ -35,7 +35,7 @@ Pinout by Pin Number:
|A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | | |A13 | |DIFFM |IO_L01P_0 |UNUSED | |0 | | | | | | | | |
|A14 | | |TDO | | | | | | | | | | | | |A14 | | |TDO | | | | | | | | | | | |
|B1 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | | |B1 | |DIFFS |IO_L01N_3 |UNUSED | |3 | | | | | | | | |
|B2 | |DIFFM |IO_L01P_3 |UNUSED | |3 | | | | | | | | | |B2 |POUT |IOB |IO_L01P_3 |OUTPUT |LVCMOS25* |3 |12 |SLOW |NONE** | | |LOCATED |NO |NONE |
|B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | | |B3 | |DIFFS |IO_L11N_0/HSWAP |UNUSED | |0 | | | | | | | | |
|B4 | |DIFFM |IO_L10P_0 |UNUSED | |0 | | | | | | | | | |B4 | |DIFFM |IO_L10P_0 |UNUSED | |0 | | | | | | | | |
|B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | | |B5 | |DIFFM |IO_L09P_0 |UNUSED | |0 | | | | | | | | |

45
main_par.xrpt
View file

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="par" timeStamp="Thu Feb 21 20:21:13 2013"> <application stringID="par" timeStamp="Fri Feb 22 15:42:16 2013">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@ -63,17 +63,17 @@
</task> </task>
<task stringID="PAR_DEVICE_UTILIZATION"> <task stringID="PAR_DEVICE_UTILIZATION">
<section stringID="PAR_DESIGN_SUMMARY"> <section stringID="PAR_DESIGN_SUMMARY">
<item AVAILABLE="2448" dataType="int" stringID="PAR_SLICES" value="52"></item> <item AVAILABLE="2448" dataType="int" stringID="PAR_SLICES" value="318"></item>
</section> </section>
</task> </task>
<task stringID="PAR_PAR"> <task stringID="PAR_PAR">
<section stringID="PAR_DESIGN_SUMMARY"> <section stringID="PAR_DESIGN_SUMMARY">
<item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="10 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_ROUTER" value="15 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="9 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_ROUTER" value="14 secs "/>
<item dataType="int" stringID="PAR_UNROUTES" value="0"/> <item dataType="int" stringID="PAR_UNROUTES" value="0"/>
<item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/> <item dataType="float" stringID="PAR_TIMING_SCORE" value="0.000000"/>
<item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="10 secs "/> <item stringID="PAR_REAL_TIME_COMPLETION_PAR" value="15 secs "/>
<item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="9 secs "/> <item stringID="PAR_CPU_TIME_COMPLETION_PAR" value="15 secs "/>
</section> </section>
</task> </task>
<task stringID="PAR_par"> <task stringID="PAR_par">
@ -88,21 +88,30 @@
<column label="Net Skew(ns)" stringID="NET_SKEW"/> <column label="Net Skew(ns)" stringID="NET_SKEW"/>
<column label="Max Delay(ns)" stringID="MAX_DELAY"/> <column label="Max Delay(ns)" stringID="MAX_DELAY"/>
<row stringID="row" value="1"> <row stringID="row" value="1">
<item label="Clock Net" stringID="CLOCK_NET" value="VGADriver/FRAME"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X1Y10"/>
<item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="43.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.038000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.100000"/>
</row>
<row stringID="row" value="2">
<item label="Clock Net" stringID="CLOCK_NET" value="CLK_BUFGP"/> <item label="Clock Net" stringID="CLOCK_NET" value="CLK_BUFGP"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/> <item label="Resource" stringID="RESOURCE" value="BUFGMUX_X2Y1"/>
<item label="Locked" stringID="LOCKED" value="No"/> <item label="Locked" stringID="LOCKED" value="No"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="25.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="39.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.037000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.038000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.098000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="0.101000"/>
</row> </row>
<row stringID="row" value="2"> <row stringID="row" value="3">
<item label="Clock Net" stringID="CLOCK_NET" value="VGADriver/W"/> <item label="Clock Net" stringID="CLOCK_NET" value="VGADriver/W"/>
<item label="Routed" stringID="ROUTED" value="ROUTED"/> <item label="Routed" stringID="ROUTED" value="ROUTED"/>
<item label="Resource" stringID="RESOURCE" value="Local"/> <item label="Resource" stringID="RESOURCE" value="Local"/>
<item dataType="float" label="Fanout" stringID="FANOUT" value="2.000000"/> <item dataType="float" label="Fanout" stringID="FANOUT" value="1.000000"/>
<item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/> <item dataType="float" label="Net Skew(ns)" stringID="NET_SKEW" value="0.000000"/>
<item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.219000"/> <item dataType="float" label="Max Delay(ns)" stringID="MAX_DELAY" value="1.110000"/>
</row> </row>
</table> </table>
</section> </section>
@ -210,10 +219,18 @@
</row> </row>
<row stringID="row" value="16"> <row stringID="row" value="16">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="B2"/> <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="B2"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="DIFFM"/> <item label="Signal&#xA;Name" stringID="Signal_Name" value="POUT"/>
<item label="Pin&#xA;Usage" stringID="Pin_Usage" value="IOB"/>
<item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L01P_3"/> <item label="Pin&#xA;Name" sort="smart" stringID="Pin_Name" value="IO_L01P_3"/>
<item stringID="Direction" value="UNUSED"/> <item stringID="Direction" value="OUTPUT"/>
<item label="IO&#xA;Standard" sort="smart" stringID="IO_Standard" value="LVCMOS25*"/>
<item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/> <item label="IO Bank&#xA;Number" stringID="IO_Bank_Number" value="3"/>
<item label="Drive&#xA;(mA)" stringID="Drive" value="12"/>
<item label="Slew&#xA;Rate" stringID="Slew_Rate" value="SLOW"/>
<item label="Termination" stringID="Termination" value="NONE**"/>
<item label="Constraint" stringID="Constraint" value="LOCATED"/>
<item label="IO&#xA;Register" stringID="IO_Register" value="NO"/>
<item label="Signal&#xA;Integrity" stringID="Signal_Integrity" value="NONE"/>
</row> </row>
<row stringID="row" value="17"> <row stringID="row" value="17">
<item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="B3"/> <item label="Pin&#xA;Number" sort="smart" stringID="Pin_Number" value="B3"/>

56
main_summary.html
View file

@ -2,7 +2,7 @@
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'> <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (02/21/2013 - 20:21:36)</B></TD></TR> <TD ALIGN=CENTER COLSPAN='4'><B>main Project Status (02/22/2013 - 14:37:18)</B></TD></TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD> <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>pong.xise</TD> <TD>pong.xise</TD>
@ -25,7 +25,7 @@ No Errors</TD>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.1</TD> <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.1</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/*.xmsgs?&DataKey=Warning'>4 Warnings (0 new)</A></TD> <TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/*.xmsgs?&DataKey=Warning'>15 Warnings (15 new)</A></TD>
</TR> </TR>
<TR ALIGN=LEFT> <TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD> <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@ -60,61 +60,61 @@ System Settings</A>
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD> <TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD><B>Utilization</B></TD><TD COLSPAN='2'><B>Note(s)</B></TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number Slice Registers</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number Slice Registers</TD>
<TD ALIGN=RIGHT>47</TD> <TD ALIGN=RIGHT>97</TD>
<TD ALIGN=RIGHT>4,896</TD> <TD ALIGN=RIGHT>4,896</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>1%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Flip Flops</TD>
<TD ALIGN=RIGHT>45</TD> <TD ALIGN=RIGHT>96</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as Latches</TD>
<TD ALIGN=RIGHT>2</TD> <TD ALIGN=RIGHT>1</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>58</TD> <TD ALIGN=RIGHT>376</TD>
<TD ALIGN=RIGHT>4,896</TD> <TD ALIGN=RIGHT>4,896</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>7%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of occupied Slices</TD>
<TD ALIGN=RIGHT>52</TD> <TD ALIGN=RIGHT>249</TD>
<TD ALIGN=RIGHT>2,448</TD> <TD ALIGN=RIGHT>2,448</TD>
<TD ALIGN=RIGHT>2%</TD> <TD ALIGN=RIGHT>10%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing only related logic</TD>
<TD ALIGN=RIGHT>52</TD> <TD ALIGN=RIGHT>249</TD>
<TD ALIGN=RIGHT>52</TD> <TD ALIGN=RIGHT>249</TD>
<TD ALIGN=RIGHT>100%</TD> <TD ALIGN=RIGHT>100%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number of Slices containing unrelated logic</TD>
<TD ALIGN=RIGHT>0</TD> <TD ALIGN=RIGHT>0</TD>
<TD ALIGN=RIGHT>52</TD> <TD ALIGN=RIGHT>249</TD>
<TD ALIGN=RIGHT>0%</TD> <TD ALIGN=RIGHT>0%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Total Number of 4 input LUTs</TD>
<TD ALIGN=RIGHT>92</TD> <TD ALIGN=RIGHT>450</TD>
<TD ALIGN=RIGHT>4,896</TD> <TD ALIGN=RIGHT>4,896</TD>
<TD ALIGN=RIGHT>1%</TD> <TD ALIGN=RIGHT>9%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as logic</TD>
<TD ALIGN=RIGHT>58</TD> <TD ALIGN=RIGHT>376</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>&nbsp;&nbsp;&nbsp;&nbsp;Number used as a route-thru</TD>
<TD ALIGN=RIGHT>34</TD> <TD ALIGN=RIGHT>74</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
@ -126,13 +126,13 @@ System Settings</A>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of BUFGMUXs</TD>
<TD ALIGN=RIGHT>1</TD> <TD ALIGN=RIGHT>2</TD>
<TD ALIGN=RIGHT>24</TD> <TD ALIGN=RIGHT>24</TD>
<TD ALIGN=RIGHT>4%</TD> <TD ALIGN=RIGHT>8%</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
</TR> </TR>
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD> <TR ALIGN=RIGHT><TD ALIGN=LEFT>Average Fanout of Non-Clock Nets</TD>
<TD ALIGN=RIGHT>2.67</TD> <TD ALIGN=RIGHT>2.66</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD>&nbsp;</TD> <TD>&nbsp;</TD>
<TD COLSPAN='2'>&nbsp;</TD> <TD COLSPAN='2'>&nbsp;</TD>
@ -169,21 +169,21 @@ System Settings</A>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR> <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:01 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Warning'>3 Warnings (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Info'>5 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:36:37 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Warning'>15 Warnings (15 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/xst.xmsgs?&DataKey=Info'>3 Infos (3 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bld'>Translation Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:06 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bld'>Translation Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:36:43 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:11 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/map.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main_map.mrp'>Map Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:36:48 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/map.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:23 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='C:/fpga/pong\_xmsgs/par.xmsgs?&DataKey=Warning'>1 Warning (0 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.par'>Place and Route Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:37:04 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/par.xmsgs?&DataKey=Info'>2 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR> <TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:27 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.twr'>Post-PAR Static Timing Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:37:07 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='C:/fpga/pong\_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Thu Feb 21 20:21:32 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\main.bgn'>Bitgen Report</A></TD><TD>Current</TD><TD>Fri Feb 22 14:37:14 2013</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
</TABLE> </TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> &nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Feb 21 20:21:32 2013</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\usage_statistics_webtalk.html'>WebTalk Report</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Feb 22 14:37:14 2013</TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\webtalk.log'>WebTalk Log File</A></TD><TD>Current</TD><TD COLSPAN='2'>Thu Feb 21 20:21:36 2013</TD></TR> <TR ALIGN=LEFT><TD><A HREF_DISABLED='C:/fpga/pong\webtalk.log'>WebTalk Log File</A></TD><TD>Out of Date</TD><TD COLSPAN='2'>Fri Feb 22 14:37:18 2013</TD></TR>
</TABLE> </TABLE>
<br><center><b>Date Generated:</b> 02/21/2013 - 20:21:36</center> <br><center><b>Date Generated:</b> 02/22/2013 - 14:39:05</center>
</BODY></HTML> </BODY></HTML>

2
main_summary.xml
View file

@ -4,7 +4,7 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DesignSummary rev="116"> <DesignSummary rev="267">
<CmdHistory> <CmdHistory>
</CmdHistory> </CmdHistory>
</DesignSummary> </DesignSummary>

696
main_usage.xml
View file

@ -4,447 +4,447 @@
changes made to this file may result in unpredictable changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. --> users do not edit the contents of this file. -->
<DeviceUsageSummary rev="116"> <DeviceUsageSummary rev="267">
<DesignStatistics TimeStamp="Thu Feb 21 20:21:32 2013"><group name="NetStatistics"> <DesignStatistics TimeStamp="Fri Feb 22 15:42:40 2013"><group name="NetStatistics">
<item name="NumNets_Active" rev="116"> <item name="NumNets_Active" rev="267">
<attrib name="value" value="134"/></item> <attrib name="value" value="643"/></item>
<item name="NumNets_Gnd" rev="116"> <item name="NumNets_Gnd" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNets_Vcc" rev="116"> <item name="NumNets_Vcc" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_CLKPIN" rev="116"> <item name="NumNodesOfType_Active_CLKPIN" rev="267">
<attrib name="value" value="27"/></item> <attrib name="value" value="83"/></item>
<item name="NumNodesOfType_Active_CNTRLPIN" rev="116"> <item name="NumNodesOfType_Active_CNTRLPIN" rev="267">
<attrib name="value" value="29"/></item> <attrib name="value" value="74"/></item>
<item name="NumNodesOfType_Active_DOUBLE" rev="116"> <item name="NumNodesOfType_Active_DOUBLE" rev="267">
<attrib name="value" value="151"/></item> <attrib name="value" value="1121"/></item>
<item name="NumNodesOfType_Active_DUMMY" rev="116"> <item name="NumNodesOfType_Active_DUMMY" rev="267">
<attrib name="value" value="213"/></item> <attrib name="value" value="1374"/></item>
<item name="NumNodesOfType_Active_DUMMYESC" rev="116"> <item name="NumNodesOfType_Active_DUMMYESC" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_GLOBAL" rev="116"> <item name="NumNodesOfType_Active_GLOBAL" rev="267">
<attrib name="value" value="14"/></item> <attrib name="value" value="45"/></item>
<item name="NumNodesOfType_Active_HFULLHEX" rev="116"> <item name="NumNodesOfType_Active_HFULLHEX" rev="267">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_HUNIHEX" rev="116">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Active_INPUT" rev="116">
<attrib name="value" value="246"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="116">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="116">
<attrib name="value" value="111"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="116">
<attrib name="value" value="114"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="116">
<attrib name="value" value="52"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="116">
<attrib name="value" value="7"/></item>
<item name="NumNodesOfType_Active_VLONG" rev="116">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="116">
<attrib name="value" value="6"/></item>
<item name="NumNodesOfType_Gnd_DOUBLE" rev="116">
<attrib name="value" value="10"/></item>
<item name="NumNodesOfType_Gnd_INPUT" rev="116">
<attrib name="value" value="12"/></item> <attrib name="value" value="12"/></item>
<item name="NumNodesOfType_Gnd_OMUX" rev="116"> <item name="NumNodesOfType_Active_HLONG" rev="267">
<attrib name="value" value="6"/></item> <attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Gnd_OUTPUT" rev="116"> <item name="NumNodesOfType_Active_HUNIHEX" rev="267">
<attrib name="value" value="8"/></item> <attrib name="value" value="83"/></item>
<item name="NumNodesOfType_Gnd_PREBXBY" rev="116"> <item name="NumNodesOfType_Active_INPUT" rev="267">
<attrib name="value" value="5"/></item> <attrib name="value" value="1587"/></item>
<item name="NumNodesOfType_Active_IOBOUTPUT" rev="267">
<attrib name="value" value="1"/></item>
<item name="NumNodesOfType_Active_OMUX" rev="267">
<attrib name="value" value="518"/></item>
<item name="NumNodesOfType_Active_OUTPUT" rev="267">
<attrib name="value" value="626"/></item>
<item name="NumNodesOfType_Active_PREBXBY" rev="267">
<attrib name="value" value="339"/></item>
<item name="NumNodesOfType_Active_VFULLHEX" rev="267">
<attrib name="value" value="28"/></item>
<item name="NumNodesOfType_Active_VUNIHEX" rev="267">
<attrib name="value" value="64"/></item>
<item name="NumNodesOfType_Vcc_CNTRLPIN" rev="267">
<attrib name="value" value="2"/></item>
<item name="NumNodesOfType_Vcc_INPUT" rev="267">
<attrib name="value" value="32"/></item>
<item name="NumNodesOfType_Vcc_PREBXBY" rev="267">
<attrib name="value" value="32"/></item>
<item name="NumNodesOfType_Vcc_VCCOUT" rev="267">
<attrib name="value" value="33"/></item>
</group> </group>
<group name="MiscellaneousStatistics"> <group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="115"> <item name="AGG_BONDED_IO" rev="266">
<attrib name="value" value="19"/></item> <attrib name="value" value="20"/></item>
<item name="AGG_IO" rev="115"> <item name="AGG_IO" rev="266">
<attrib name="value" value="19"/></item> <attrib name="value" value="20"/></item>
<item name="AGG_SLICE" rev="115"> <item name="AGG_SLICE" rev="266">
<attrib name="value" value="52"/></item> <attrib name="value" value="318"/></item>
<item name="NUM_4_INPUT_LUT" rev="115"> <item name="NUM_4_INPUT_LUT" rev="266">
<attrib name="value" value="92"/></item> <attrib name="value" value="584"/></item>
<item name="NUM_BONDED_IBUF" rev="115"> <item name="NUM_BONDED_IBUF" rev="266">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="NUM_BONDED_IOB" rev="115"> <item name="NUM_BONDED_IOB" rev="266">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
<item name="NUM_BUFGMUX" rev="115"> <item name="NUM_BUFGMUX" rev="266">
<attrib name="value" value="1"/></item>
<item name="NUM_CYMUX" rev="115">
<attrib name="value" value="45"/></item>
<item name="NUM_LUT_RT" rev="115">
<attrib name="value" value="34"/></item>
<item name="NUM_SLICEL" rev="115">
<attrib name="value" value="52"/></item>
<item name="NUM_SLICE_FF" rev="115">
<attrib name="value" value="45"/></item>
<item name="NUM_SLICE_LATCH" rev="115">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
<item name="NUM_XOR" rev="115"> <item name="NUM_CYMUX" rev="266">
<attrib name="value" value="50"/></item> <attrib name="value" value="402"/></item>
<item name="NUM_LUT_RT" rev="266">
<attrib name="value" value="76"/></item>
<item name="NUM_SLICEL" rev="266">
<attrib name="value" value="318"/></item>
<item name="NUM_SLICE_FF" rev="266">
<attrib name="value" value="145"/></item>
<item name="NUM_SLICE_LATCH" rev="266">
<attrib name="value" value="1"/></item>
<item name="NUM_XOR" rev="266">
<attrib name="value" value="246"/></item>
</group> </group>
<group name="SiteStatistics"> <group name="SiteStatistics">
<item name="IBUF-DIFFMI" rev="116"> <item name="IBUF-DIFFMI" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="IOB-DIFFM" rev="116"> <item name="IOB-DIFFM" rev="267">
<attrib name="value" value="8"/></item>
<item name="IOB-DIFFS" rev="116">
<attrib name="value" value="9"/></item> <attrib name="value" value="9"/></item>
<item name="SLICEL-SLICEM" rev="116"> <item name="IOB-DIFFS" rev="267">
<attrib name="value" value="21"/></item> <attrib name="value" value="9"/></item>
<item name="SLICEL-SLICEM" rev="267">
<attrib name="value" value="89"/></item>
</group> </group>
</DesignStatistics> </DesignStatistics>
<DeviceUsage TimeStamp="Thu Feb 21 20:21:32 2013"><group name="SiteSummary"> <DeviceUsage TimeStamp="Fri Feb 22 15:42:40 2013"><group name="SiteSummary">
<item name="BUFGMUX" rev="116"> <item name="BUFGMUX" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="BUFGMUX_GCLKMUX" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="BUFGMUX_GCLK_BUFFER" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IBUF" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IBUF_INBUF" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IBUF_PAD" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="IOB" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="IOB_OUTBUF" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="IOB_PAD" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item>
<item name="SLICEL" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="52"/></item>
<item name="SLICEL_C1VDD" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="SLICEL_C2VDD" rev="116">
<attrib name="total" value="1000000"/><attrib name="used" value="2"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="SLICEL_CYMUXF" rev="116"> <item name="BUFGMUX_GCLKMUX" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="SLICEL_CYMUXG" rev="116"> <item name="BUFGMUX_GCLK_BUFFER" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="20"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="2"/></item>
<item name="SLICEL_F" rev="116"> <item name="IBUF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="48"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICEL_F5MUX" rev="116"> <item name="IBUF_INBUF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="3"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICEL_FFX" rev="116"> <item name="IBUF_PAD" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="22"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="1"/></item>
<item name="SLICEL_FFY" rev="116"> <item name="IOB" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="SLICEL_G" rev="116"> <item name="IOB_OUTBUF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="44"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="SLICEL_GNDF" rev="116"> <item name="IOB_PAD" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="19"/></item>
<item name="SLICEL_GNDG" rev="116"> <item name="SLICEL" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="18"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="318"/></item>
<item name="SLICEL_XORF" rev="116"> <item name="SLICEL_C1VDD" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="39"/></item>
<item name="SLICEL_XORG" rev="116"> <item name="SLICEL_C2VDD" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="25"/></item> <attrib name="total" value="1000000"/><attrib name="used" value="35"/></item>
<item name="SLICEL_CYMUXF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="216"/></item>
<item name="SLICEL_CYMUXG" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="186"/></item>
<item name="SLICEL_F" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="301"/></item>
<item name="SLICEL_F5MUX" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="7"/></item>
<item name="SLICEL_FFX" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="69"/></item>
<item name="SLICEL_FFY" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="77"/></item>
<item name="SLICEL_G" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="283"/></item>
<item name="SLICEL_GNDF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="82"/></item>
<item name="SLICEL_GNDG" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="58"/></item>
<item name="SLICEL_XORF" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="127"/></item>
<item name="SLICEL_XORG" rev="267">
<attrib name="total" value="1000000"/><attrib name="used" value="119"/></item>
</group> </group>
</DeviceUsage> </DeviceUsage>
<ReportConfigData TimeStamp="Thu Feb 21 20:21:32 2013"><group name="IBUF_PAD"> <ReportConfigData TimeStamp="Fri Feb 22 15:42:40 2013"><group name="IBUF_PAD">
<item name="IOATTRBOX" rev="116"> <item name="IOATTRBOX" rev="267">
<attrib name="LVCMOS25" value="1"/></item> <attrib name="LVCMOS25" value="1"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="BX" rev="116"> <item name="BX" rev="267">
<attrib name="BX_INV" value="0"/><attrib name="BX" value="8"/></item> <attrib name="BX_INV" value="4"/><attrib name="BX" value="47"/></item>
<item name="BY" rev="116"> <item name="BY" rev="267">
<attrib name="BY" value="3"/><attrib name="BY_INV" value="0"/></item> <attrib name="BY" value="11"/><attrib name="BY_INV" value="3"/></item>
<item name="CE" rev="116"> <item name="CE" rev="267">
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item> <attrib name="CE" value="44"/><attrib name="CE_INV" value="0"/></item>
<item name="CIN" rev="116"> <item name="CIN" rev="267">
<attrib name="CIN_INV" value="0"/><attrib name="CIN" value="20"/></item> <attrib name="CIN_INV" value="0"/><attrib name="CIN" value="182"/></item>
<item name="CLK" rev="116"> <item name="CLK" rev="267">
<attrib name="CLK" value="25"/><attrib name="CLK_INV" value="2"/></item> <attrib name="CLK" value="82"/><attrib name="CLK_INV" value="1"/></item>
<item name="SR" rev="116"> <item name="SR" rev="267">
<attrib name="SR" value="14"/><attrib name="SR_INV" value="0"/></item> <attrib name="SR" value="16"/><attrib name="SR_INV" value="14"/></item>
</group> </group>
<group name="IOB_OUTBUF"> <group name="IOB_OUTBUF">
<item name="IN" rev="116"> <item name="IN" rev="267">
<attrib name="IN_INV" value="0"/><attrib name="IN" value="18"/></item> <attrib name="IN_INV" value="0"/><attrib name="IN" value="19"/></item>
</group> </group>
<group name="SLICEL_CYMUXF"> <group name="SLICEL_CYMUXF">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="0" value="25"/><attrib name="0_INV" value="0"/></item> <attrib name="0" value="216"/><attrib name="0_INV" value="0"/></item>
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="1_INV" value="0"/><attrib name="1" value="25"/></item> <attrib name="1_INV" value="2"/><attrib name="1" value="214"/></item>
</group> </group>
<group name="SLICEL_CYMUXG"> <group name="SLICEL_CYMUXG">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="0" value="20"/><attrib name="0_INV" value="0"/></item> <attrib name="0" value="186"/><attrib name="0_INV" value="0"/></item>
</group> </group>
<group name="BUFGMUX_GCLKMUX"> <group name="BUFGMUX_GCLKMUX">
<item name="DISABLE_ATTR" rev="116"> <item name="DISABLE_ATTR" rev="267">
<attrib name="LOW" value="1"/></item> <attrib name="LOW" value="2"/></item>
<item name="S" rev="116"> <item name="S" rev="267">
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item> <attrib name="S_INV" value="2"/><attrib name="S" value="0"/></item>
</group> </group>
<group name="SLICEL_FFX"> <group name="SLICEL_FFX">
<item name="CE" rev="116"> <item name="CE" rev="267">
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item> <attrib name="CE" value="38"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="116"> <item name="CK" rev="267">
<attrib name="CK" value="21"/><attrib name="CK_INV" value="1"/></item> <attrib name="CK" value="68"/><attrib name="CK_INV" value="1"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="D" value="22"/><attrib name="D_INV" value="0"/></item> <attrib name="D" value="67"/><attrib name="D_INV" value="2"/></item>
<item name="FFX_INIT_ATTR" rev="116"> <item name="FFX_INIT_ATTR" rev="267">
<attrib name="INIT0" value="22"/></item> <attrib name="INIT0" value="63"/><attrib name="INIT1" value="6"/></item>
<item name="FFX_SR_ATTR" rev="116"> <item name="FFX_SR_ATTR" rev="267">
<attrib name="SRLOW" value="22"/></item> <attrib name="SRLOW" value="69"/></item>
<item name="LATCH_OR_FF" rev="116"> <item name="LATCH_OR_FF" rev="267">
<attrib name="FF" value="21"/><attrib name="LATCH" value="1"/></item> <attrib name="FF" value="68"/><attrib name="LATCH" value="1"/></item>
<item name="SR" rev="116"> <item name="SR" rev="267">
<attrib name="SR" value="10"/><attrib name="SR_INV" value="0"/></item> <attrib name="SR" value="10"/><attrib name="SR_INV" value="13"/></item>
<item name="SYNC_ATTR" rev="116"> <item name="SYNC_ATTR" rev="267">
<attrib name="ASYNC" value="12"/><attrib name="SYNC" value="10"/></item> <attrib name="ASYNC" value="46"/><attrib name="SYNC" value="23"/></item>
</group> </group>
<group name="SLICEL_XORF"> <group name="SLICEL_XORF">
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="1_INV" value="0"/><attrib name="1" value="25"/></item> <attrib name="1_INV" value="2"/><attrib name="1" value="125"/></item>
</group> </group>
<group name="SLICEL_FFY"> <group name="SLICEL_FFY">
<item name="CE" rev="116"> <item name="CE" rev="267">
<attrib name="CE" value="15"/><attrib name="CE_INV" value="0"/></item> <attrib name="CE" value="42"/><attrib name="CE_INV" value="0"/></item>
<item name="CK" rev="116"> <item name="CK" rev="267">
<attrib name="CK" value="24"/><attrib name="CK_INV" value="1"/></item> <attrib name="CK" value="77"/><attrib name="CK_INV" value="0"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="D" value="25"/><attrib name="D_INV" value="0"/></item> <attrib name="D" value="74"/><attrib name="D_INV" value="3"/></item>
<item name="FFY_INIT_ATTR" rev="116"> <item name="FFY_INIT_ATTR" rev="267">
<attrib name="INIT0" value="24"/><attrib name="INIT1" value="1"/></item> <attrib name="INIT0" value="67"/><attrib name="INIT1" value="10"/></item>
<item name="FFY_SR_ATTR" rev="116"> <item name="FFY_SR_ATTR" rev="267">
<attrib name="SRLOW" value="24"/><attrib name="SRHIGH" value="1"/></item> <attrib name="SRLOW" value="77"/></item>
<item name="LATCH_OR_FF" rev="116"> <item name="LATCH_OR_FF" rev="267">
<attrib name="FF" value="24"/><attrib name="LATCH" value="1"/></item> <attrib name="FF" value="77"/></item>
<item name="SR" rev="116"> <item name="SR" rev="267">
<attrib name="SR" value="14"/><attrib name="SR_INV" value="0"/></item> <attrib name="SR" value="16"/><attrib name="SR_INV" value="13"/></item>
<item name="SYNC_ATTR" rev="116"> <item name="SYNC_ATTR" rev="267">
<attrib name="ASYNC" value="11"/><attrib name="SYNC" value="14"/></item> <attrib name="ASYNC" value="48"/><attrib name="SYNC" value="29"/></item>
</group> </group>
<group name="IOB_PAD"> <group name="IOB_PAD">
<item name="DRIVEATTRBOX" rev="116"> <item name="DRIVEATTRBOX" rev="267">
<attrib name="8" value="10"/><attrib name="12" value="8"/></item> <attrib name="8" value="10"/><attrib name="12" value="9"/></item>
<item name="IOATTRBOX" rev="116"> <item name="IOATTRBOX" rev="267">
<attrib name="LVCMOS25" value="8"/><attrib name="LVCMOS33" value="10"/></item> <attrib name="LVCMOS25" value="9"/><attrib name="LVCMOS33" value="10"/></item>
<item name="SLEW" rev="116"> <item name="SLEW" rev="267">
<attrib name="SLOW" value="8"/><attrib name="FAST" value="10"/></item> <attrib name="SLOW" value="9"/><attrib name="FAST" value="10"/></item>
</group> </group>
<group name="IOB"> <group name="IOB">
<item name="O1" rev="116"> <item name="O1" rev="267">
<attrib name="O1_INV" value="0"/><attrib name="O1" value="18"/></item> <attrib name="O1_INV" value="0"/><attrib name="O1" value="19"/></item>
</group> </group>
<group name="BUFGMUX"> <group name="BUFGMUX">
<item name="S" rev="116"> <item name="S" rev="267">
<attrib name="S_INV" value="1"/><attrib name="S" value="0"/></item> <attrib name="S_INV" value="2"/><attrib name="S" value="0"/></item>
</group> </group>
<group name="SLICEL_F5MUX"> <group name="SLICEL_F5MUX">
<item name="S0" rev="116"> <item name="S0" rev="267">
<attrib name="S0" value="3"/><attrib name="S0_INV" value="0"/></item> <attrib name="S0" value="7"/><attrib name="S0_INV" value="0"/></item>
</group> </group>
</ReportConfigData> </ReportConfigData>
<ReportPinData TimeStamp="Thu Feb 21 20:21:32 2013"><group name="IBUF_PAD"> <ReportPinData TimeStamp="Fri Feb 22 15:42:40 2013"><group name="IBUF_PAD">
<item name="PAD" rev="116"> <item name="PAD" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
</group> </group>
<group name="IBUF_INBUF"> <group name="IBUF_INBUF">
<item name="IN" rev="116"> <item name="IN" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
</group> </group>
<group name="SLICEL"> <group name="SLICEL">
<item name="BX" rev="116"> <item name="BX" rev="267">
<attrib name="value" value="8"/></item> <attrib name="value" value="51"/></item>
<item name="BY" rev="116"> <item name="BY" rev="267">
<attrib name="value" value="3"/></item>
<item name="CE" rev="116">
<attrib name="value" value="15"/></item>
<item name="CIN" rev="116">
<attrib name="value" value="20"/></item>
<item name="CLK" rev="116">
<attrib name="value" value="27"/></item>
<item name="COUT" rev="116">
<attrib name="value" value="20"/></item>
<item name="F1" rev="116">
<attrib name="value" value="46"/></item>
<item name="F2" rev="116">
<attrib name="value" value="23"/></item>
<item name="F3" rev="116">
<attrib name="value" value="23"/></item>
<item name="F4" rev="116">
<attrib name="value" value="19"/></item>
<item name="G1" rev="116">
<attrib name="value" value="44"/></item>
<item name="G2" rev="116">
<attrib name="value" value="22"/></item>
<item name="G3" rev="116">
<attrib name="value" value="20"/></item>
<item name="G4" rev="116">
<attrib name="value" value="15"/></item>
<item name="SR" rev="116">
<attrib name="value" value="14"/></item> <attrib name="value" value="14"/></item>
<item name="X" rev="116"> <item name="CE" rev="267">
<attrib name="value" value="26"/></item> <attrib name="value" value="44"/></item>
<item name="XQ" rev="116"> <item name="CIN" rev="267">
<attrib name="value" value="22"/></item> <attrib name="value" value="182"/></item>
<item name="Y" rev="116"> <item name="CLK" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="83"/></item>
<item name="YQ" rev="116"> <item name="COUT" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="186"/></item>
<item name="F1" rev="267">
<attrib name="value" value="299"/></item>
<item name="F2" rev="267">
<attrib name="value" value="226"/></item>
<item name="F3" rev="267">
<attrib name="value" value="104"/></item>
<item name="F4" rev="267">
<attrib name="value" value="73"/></item>
<item name="G1" rev="267">
<attrib name="value" value="282"/></item>
<item name="G2" rev="267">
<attrib name="value" value="216"/></item>
<item name="G3" rev="267">
<attrib name="value" value="103"/></item>
<item name="G4" rev="267">
<attrib name="value" value="68"/></item>
<item name="SR" rev="267">
<attrib name="value" value="30"/></item>
<item name="X" rev="267">
<attrib name="value" value="139"/></item>
<item name="XB" rev="267">
<attrib name="value" value="16"/></item>
<item name="XQ" rev="267">
<attrib name="value" value="69"/></item>
<item name="Y" rev="267">
<attrib name="value" value="133"/></item>
<item name="YQ" rev="267">
<attrib name="value" value="77"/></item>
</group> </group>
<group name="IOB_OUTBUF"> <group name="IOB_OUTBUF">
<item name="IN" rev="116"> <item name="IN" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
</group> </group>
<group name="SLICEL_CYMUXF"> <group name="SLICEL_CYMUXF">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="216"/></item>
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="216"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="216"/></item>
<item name="S0" rev="116"> <item name="S0" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="216"/></item>
</group> </group>
<group name="SLICEL_CYMUXG"> <group name="SLICEL_CYMUXG">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="186"/></item>
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="186"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="186"/></item>
<item name="S0" rev="116"> <item name="S0" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="186"/></item>
</group> </group>
<group name="BUFGMUX_GCLKMUX"> <group name="BUFGMUX_GCLKMUX">
<item name="I0" rev="116"> <item name="I0" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
<item name="S" rev="116"> <item name="S" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="SLICEL_C1VDD"> <group name="SLICEL_C1VDD">
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="value" value="7"/></item> <attrib name="value" value="39"/></item>
</group> </group>
<group name="IBUF"> <group name="IBUF">
<item name="I" rev="116"> <item name="I" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
<item name="PAD" rev="116"> <item name="PAD" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="1"/></item>
</group> </group>
<group name="SLICEL_FFX"> <group name="SLICEL_FFX">
<item name="CE" rev="116"> <item name="CE" rev="267">
<attrib name="value" value="15"/></item> <attrib name="value" value="38"/></item>
<item name="CK" rev="116"> <item name="CK" rev="267">
<attrib name="value" value="22"/></item> <attrib name="value" value="69"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="value" value="22"/></item> <attrib name="value" value="69"/></item>
<item name="Q" rev="116"> <item name="Q" rev="267">
<attrib name="value" value="22"/></item> <attrib name="value" value="69"/></item>
<item name="SR" rev="116"> <item name="SR" rev="267">
<attrib name="value" value="10"/></item> <attrib name="value" value="23"/></item>
</group> </group>
<group name="SLICEL_XORF"> <group name="SLICEL_XORF">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="127"/></item>
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="127"/></item>
<item name="O" rev="116"> <item name="O" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="127"/></item>
</group> </group>
<group name="SLICEL_FFY"> <group name="SLICEL_FFY">
<item name="CE" rev="116"> <item name="CE" rev="267">
<attrib name="value" value="15"/></item> <attrib name="value" value="42"/></item>
<item name="CK" rev="116"> <item name="CK" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="77"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="77"/></item>
<item name="Q" rev="116"> <item name="Q" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="77"/></item>
<item name="SR" rev="116"> <item name="SR" rev="267">
<attrib name="value" value="14"/></item> <attrib name="value" value="29"/></item>
</group> </group>
<group name="SLICEL_XORG"> <group name="SLICEL_XORG">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="119"/></item>
<item name="1" rev="116"> <item name="1" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="119"/></item>
<item name="O" rev="116"> <item name="O" rev="267">
<attrib name="value" value="25"/></item> <attrib name="value" value="119"/></item>
</group> </group>
<group name="IOB_PAD"> <group name="IOB_PAD">
<item name="PAD" rev="116"> <item name="PAD" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
</group> </group>
<group name="IOB"> <group name="IOB">
<item name="O1" rev="116"> <item name="O1" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
<item name="PAD" rev="116"> <item name="PAD" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="19"/></item>
</group> </group>
<group name="BUFGMUX"> <group name="BUFGMUX">
<item name="I0" rev="116"> <item name="I0" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
<item name="O" rev="116"> <item name="O" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
<item name="S" rev="116"> <item name="S" rev="267">
<attrib name="value" value="1"/></item>
</group>
<group name="SLICEL_C2VDD">
<item name="1" rev="116">
<attrib name="value" value="2"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="SLICEL_C2VDD">
<item name="1" rev="267">
<attrib name="value" value="35"/></item>
</group>
<group name="BUFGMUX_GCLK_BUFFER"> <group name="BUFGMUX_GCLK_BUFFER">
<item name="IN" rev="116"> <item name="IN" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="1"/></item> <attrib name="value" value="2"/></item>
</group> </group>
<group name="SLICEL_F"> <group name="SLICEL_F">
<item name="A1" rev="116"> <item name="A1" rev="267">
<attrib name="value" value="46"/></item> <attrib name="value" value="297"/></item>
<item name="A2" rev="116"> <item name="A2" rev="267">
<attrib name="value" value="23"/></item> <attrib name="value" value="226"/></item>
<item name="A3" rev="116"> <item name="A3" rev="267">
<attrib name="value" value="23"/></item> <attrib name="value" value="104"/></item>
<item name="A4" rev="116"> <item name="A4" rev="267">
<attrib name="value" value="19"/></item> <attrib name="value" value="73"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="value" value="48"/></item> <attrib name="value" value="301"/></item>
</group> </group>
<group name="SLICEL_F5MUX"> <group name="SLICEL_F5MUX">
<item name="F" rev="116"> <item name="F" rev="267">
<attrib name="value" value="3"/></item> <attrib name="value" value="7"/></item>
<item name="G" rev="116"> <item name="G" rev="267">
<attrib name="value" value="3"/></item> <attrib name="value" value="7"/></item>
<item name="OUT" rev="116"> <item name="OUT" rev="267">
<attrib name="value" value="3"/></item> <attrib name="value" value="7"/></item>
<item name="S0" rev="116"> <item name="S0" rev="267">
<attrib name="value" value="3"/></item> <attrib name="value" value="7"/></item>
</group> </group>
<group name="SLICEL_G"> <group name="SLICEL_G">
<item name="A1" rev="116"> <item name="A1" rev="267">
<attrib name="value" value="44"/></item> <attrib name="value" value="278"/></item>
<item name="A2" rev="116"> <item name="A2" rev="267">
<attrib name="value" value="22"/></item> <attrib name="value" value="216"/></item>
<item name="A3" rev="116"> <item name="A3" rev="267">
<attrib name="value" value="20"/></item> <attrib name="value" value="103"/></item>
<item name="A4" rev="116"> <item name="A4" rev="267">
<attrib name="value" value="15"/></item> <attrib name="value" value="68"/></item>
<item name="D" rev="116"> <item name="D" rev="267">
<attrib name="value" value="44"/></item> <attrib name="value" value="283"/></item>
</group> </group>
<group name="SLICEL_GNDF"> <group name="SLICEL_GNDF">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="82"/></item>
</group> </group>
<group name="SLICEL_GNDG"> <group name="SLICEL_GNDG">
<item name="0" rev="116"> <item name="0" rev="267">
<attrib name="value" value="18"/></item> <attrib name="value" value="58"/></item>
</group> </group>
</ReportPinData> </ReportPinData>
<CmdHistory> <CmdHistory>

1
main_vhdl.prj
View file

@ -1,2 +1,3 @@
vhdl work "C:\fpga\pong\vga.vhd" vhdl work "C:\fpga\pong\vga.vhd"
vhdl work "C:\fpga\pong\speaker.vhd"
vhdl work "C:\fpga\pong\main.vhd" vhdl work "C:\fpga\pong\main.vhd"

89
main_xst.xrpt
View file

@ -5,7 +5,7 @@
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application stringID="Xst" timeStamp="Thu Feb 21 20:20:55 2013"> <application stringID="Xst" timeStamp="Fri Feb 22 15:41:52 2013">
<section stringID="User_Env"> <section stringID="User_Env">
<table stringID="User_EnvVar"> <table stringID="User_EnvVar">
<column stringID="variable"/> <column stringID="variable"/>
@ -110,36 +110,42 @@
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/> <item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
</section> </section>
<section stringID="XST_HDL_SYNTHESIS_REPORT"> <section stringID="XST_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"> <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="24">
<item dataType="int" stringID="XST_10BIT_ADDER" value="2"/> <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/> <item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
<item dataType="int" stringID="XST_11BIT_SUBTRACTOR" value="8"/>
</item> </item>
<item dataType="int" stringID="XST_COUNTERS" value="2"> <item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/> <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_REGISTERS" value="6"> <item dataType="int" stringID="XST_ACCUMULATORS" value="4"></item>
<item dataType="int" stringID="XST_1BIT_REGISTER" value="3"/> <item dataType="int" stringID="XST_REGISTERS" value="14">
<item dataType="int" stringID="XST_1BIT_REGISTER" value="6"/>
<item dataType="int" stringID="XST_10BIT_REGISTER" value="2"/> <item dataType="int" stringID="XST_10BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_19BIT_REGISTER" value="1"/>
<item dataType="int" stringID="XST_6BIT_REGISTER" value="2"/>
<item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/> <item dataType="int" stringID="XST_8BIT_REGISTER" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_COMPARATORS" value="12"></item> <item dataType="int" stringID="XST_COMPARATORS" value="59"></item>
</section> </section>
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT"> <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORT">
<item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="4"> <item dataType="int" stringID="XST_ADDERSSUBTRACTORS" value="24">
<item dataType="int" stringID="XST_10BIT_ADDER" value="2"/> <item dataType="int" stringID="XST_10BIT_ADDER" value="2"/>
<item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/> <item dataType="int" stringID="XST_10BIT_SUBTRACTOR" value="2"/>
<item dataType="int" stringID="XST_11BIT_SUBTRACTOR" value="8"/>
</item> </item>
<item dataType="int" stringID="XST_COUNTERS" value="2"> <item dataType="int" stringID="XST_COUNTERS" value="2">
<item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/> <item dataType="int" stringID="XST_10BIT_UP_COUNTER" value="2"/>
</item> </item>
<item dataType="int" stringID="XST_REGISTERS" value="31"> <item dataType="int" stringID="XST_ACCUMULATORS" value="4"></item>
<item dataType="int" stringID="XST_FLIPFLOPS" value="31"/> <item dataType="int" stringID="XST_REGISTERS" value="115">
<item dataType="int" stringID="XST_FLIPFLOPS" value="115"/>
</item> </item>
<item dataType="int" stringID="XST_COMPARATORS" value="12"></item> <item dataType="int" stringID="XST_COMPARATORS" value="59"></item>
</section> </section>
<section stringID="XST_FINAL_REGISTER_REPORT"> <section stringID="XST_FINAL_REGISTER_REPORT">
<item dataType="int" stringID="XST_REGISTERS" value="45"> <item dataType="int" stringID="XST_REGISTERS" value="145">
<item dataType="int" stringID="XST_FLIPFLOPS" value="45"/> <item dataType="int" stringID="XST_FLIPFLOPS" value="145"/>
</item> </item>
</section> </section>
<section stringID="XST_PARTITION_REPORT"> <section stringID="XST_PARTITION_REPORT">
@ -156,56 +162,57 @@
<item stringID="XST_KEEP_HIERARCHY" value="No"/> <item stringID="XST_KEEP_HIERARCHY" value="No"/>
</section> </section>
<section stringID="XST_DESIGN_STATISTICS"> <section stringID="XST_DESIGN_STATISTICS">
<item stringID="XST_IOS" value="19"/> <item stringID="XST_IOS" value="20"/>
</section> </section>
<section stringID="XST_CELL_USAGE"> <section stringID="XST_CELL_USAGE">
<item dataType="int" stringID="XST_BELS" value="189"> <item dataType="int" stringID="XST_BELS" value="1250">
<item dataType="int" stringID="XST_GND" value="1"/> <item dataType="int" stringID="XST_GND" value="1"/>
<item dataType="int" stringID="XST_INV" value="11"/> <item dataType="int" stringID="XST_INV" value="71"/>
<item dataType="int" stringID="XST_LUT1" value="33"/> <item dataType="int" stringID="XST_LUT1" value="76"/>
<item dataType="int" stringID="XST_LUT2" value="1"/> <item dataType="int" stringID="XST_LUT2" value="225"/>
<item dataType="int" stringID="XST_LUT2L" value="1"/> <item dataType="int" stringID="XST_LUT2D" value="2"/>
<item dataType="int" stringID="XST_LUT3" value="6"/> <item dataType="int" stringID="XST_LUT2L" value="10"/>
<item dataType="int" stringID="XST_LUT3" value="65"/>
<item dataType="int" stringID="XST_LUT3L" value="3"/> <item dataType="int" stringID="XST_LUT3L" value="3"/>
<item dataType="int" stringID="XST_LUT4" value="29"/> <item dataType="int" stringID="XST_LUT4" value="127"/>
<item dataType="int" stringID="XST_LUT4D" value="1"/> <item dataType="int" stringID="XST_LUT4D" value="4"/>
<item dataType="int" stringID="XST_LUT4L" value="4"/> <item dataType="int" stringID="XST_LUT4L" value="6"/>
<item dataType="int" stringID="XST_MUXCY" value="45"/> <item dataType="int" stringID="XST_MUXCY" value="404"/>
<item dataType="int" stringID="XST_MUXF5" value="3"/> <item dataType="int" stringID="XST_MUXF5" value="7"/>
<item dataType="int" stringID="XST_VCC" value="1"/> <item dataType="int" stringID="XST_VCC" value="1"/>
<item dataType="int" stringID="XST_XORCY" value="50"/> <item dataType="int" stringID="XST_XORCY" value="248"/>
</item> </item>
<item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="47"> <item dataType="int" stringID="XST_FLIPFLOPSLATCHES" value="146">
<item dataType="int" stringID="XST_FD" value="1"/> <item dataType="int" stringID="XST_FD" value="25"/>
<item dataType="int" stringID="XST_FDE" value="20"/> <item dataType="int" stringID="XST_FDE" value="68"/>
<item dataType="int" stringID="XST_FDR" value="13"/> <item dataType="int" stringID="XST_FDR" value="40"/>
<item dataType="int" stringID="XST_FDRE" value="10"/> <item dataType="int" stringID="XST_FDRE" value="12"/>
<item dataType="int" stringID="XST_FDS" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_CLOCK_BUFFERS" value="1"> <item dataType="int" stringID="XST_CLOCK_BUFFERS" value="2">
<item dataType="int" label="-bufg" stringID="XST_BUFG" value="1"/>
<item dataType="int" stringID="XST_BUFGP" value="1"/> <item dataType="int" stringID="XST_BUFGP" value="1"/>
</item> </item>
<item dataType="int" stringID="XST_IO_BUFFERS" value="18"> <item dataType="int" stringID="XST_IO_BUFFERS" value="19">
<item dataType="int" stringID="XST_OBUF" value="18"/> <item dataType="int" stringID="XST_OBUF" value="19"/>
</item> </item>
</section> </section>
</section> </section>
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY"> <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
<item stringID="XST_SELECTED_DEVICE" value="3s250ecp132-5"/> <item stringID="XST_SELECTED_DEVICE" value="3s250ecp132-5"/>
<item AVAILABLE="2448" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="50"/> <item AVAILABLE="2448" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="314"/>
<item AVAILABLE="4896" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="47"/> <item AVAILABLE="4896" dataType="int" label="Number of Slice Flip Flops" stringID="XST_NUMBER_OF_SLICE_FLIP_FLOPS" value="146"/>
<item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="89"/> <item AVAILABLE="4896" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="589"/>
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="19"/> <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="20"/>
<item AVAILABLE="92" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="19"/> <item AVAILABLE="92" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="20"/>
<item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="1"/> <item AVAILABLE="24" dataType="int" label="Number of GCLKs" stringID="XST_NUMBER_OF_GCLKS" value="2"/>
</section> </section>
<section stringID="XST_PARTITION_RESOURCE_SUMMARY"> <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/> <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
</section> </section>
<section stringID="XST_ERRORS_STATISTICS"> <section stringID="XST_ERRORS_STATISTICS">
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_ERRORS" value="0"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="3"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_WARNINGS" value="61"/>
<item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="5"/> <item dataType="int" filtered="0" stringID="XST_NUMBER_OF_INFOS" value="4"/>
</section> </section>
</application> </application>

2
pins.ucf
View file

@ -1,5 +1,7 @@
NET "CLK" LOC = "M6"; NET "CLK" LOC = "M6";
NET "POUT" LOC = "B2";
NET "LED<0>" LOC = "M5"; NET "LED<0>" LOC = "M5";
NET "LED<1>" LOC = "M11"; NET "LED<1>" LOC = "M11";
NET "LED<2>" LOC = "P7"; NET "LED<2>" LOC = "P7";

15
pong.gise
View file

@ -104,7 +104,7 @@
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499662" xil_pn:in_ck="-4648858705064165949" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="6360702674415490423" xil_pn:start_ts="1361499654"> <transform xil_pn:end_ts="1361569323" xil_pn:in_ck="6734314912740092707" xil_pn:name="TRANEXT_xstsynthesize_spartan3e" xil_pn:prop_ck="6360702674415490423" xil_pn:start_ts="1361569310">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/> <status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
@ -123,11 +123,11 @@
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/> <outfile xil_pn:name="xst"/>
</transform> </transform>
<transform xil_pn:end_ts="1361491391" xil_pn:in_ck="4913312808198" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5369975691955938141" xil_pn:start_ts="1361491391"> <transform xil_pn:end_ts="1361566280" xil_pn:in_ck="4913312808198" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="5369975691955938141" xil_pn:start_ts="1361566280">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499667" xil_pn:in_ck="-5850685379755905679" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3050130075436025607" xil_pn:start_ts="1361499662"> <transform xil_pn:end_ts="1361569329" xil_pn:in_ck="-5850685379755905679" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="3050130075436025607" xil_pn:start_ts="1361569323">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/> <outfile xil_pn:name="_ngo"/>
@ -136,7 +136,7 @@
<outfile xil_pn:name="main.ngd"/> <outfile xil_pn:name="main.ngd"/>
<outfile xil_pn:name="main_ngdbuild.xrpt"/> <outfile xil_pn:name="main_ngdbuild.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499672" xil_pn:in_ck="-5850683973347287438" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="113730145005983477" xil_pn:start_ts="1361499667"> <transform xil_pn:end_ts="1361569334" xil_pn:in_ck="-5850683973347287438" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="113730145005983477" xil_pn:start_ts="1361569329">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/> <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
@ -149,9 +149,8 @@
<outfile xil_pn:name="main_summary.xml"/> <outfile xil_pn:name="main_summary.xml"/>
<outfile xil_pn:name="main_usage.xml"/> <outfile xil_pn:name="main_usage.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499688" xil_pn:in_ck="106600371240438923" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="3129755442398015208" xil_pn:start_ts="1361499672"> <transform xil_pn:end_ts="1361569355" xil_pn:in_ck="106600371240438923" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="3129755442398015208" xil_pn:start_ts="1361569334">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/> <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="main.ncd"/> <outfile xil_pn:name="main.ncd"/>
@ -164,7 +163,7 @@
<outfile xil_pn:name="main_pad.txt"/> <outfile xil_pn:name="main_pad.txt"/>
<outfile xil_pn:name="main_par.xrpt"/> <outfile xil_pn:name="main_par.xrpt"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499696" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1361499688"> <transform xil_pn:end_ts="1361569364" xil_pn:in_ck="4774924121320" xil_pn:name="TRANEXT_bitFile_spartan3e" xil_pn:prop_ck="-7817169320884990698" xil_pn:start_ts="1361569355">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/> <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
@ -176,7 +175,7 @@
<outfile xil_pn:name="webtalk.log"/> <outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/> <outfile xil_pn:name="webtalk_pn.xml"/>
</transform> </transform>
<transform xil_pn:end_ts="1361499688" xil_pn:in_ck="-5850869619284895250" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1361499685"> <transform xil_pn:end_ts="1361569355" xil_pn:in_ck="-5850869619284895250" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1361569352">
<status xil_pn:value="SuccessfullyRun"/> <status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/> <status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/> <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>

10
pong.xise
View file

@ -21,11 +21,19 @@
</file> </file>
<file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="main.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="pins.ucf" xil_pn:type="FILE_UCF"> <file xil_pn:name="pins.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/> <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file> </file>
<file xil_pn:name="ps2.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="56"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="speaker.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
</files> </files>
<properties> <properties>

21
ps2.vhd Normal file
View file

@ -0,0 +1,21 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PS2Driver is
port (
CLK: in std_logic;
CLR: in std_logic;
PS2C: in std_logic;
PS2D: in std_logic;
KEY: out std_logic_vector(15 downto 0)
);
end PS2Driver;
architecture Behavioral of PS2Driver is
begin
end Behavioral;

43
speaker.vhd Normal file
View file

@ -0,0 +1,43 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- period of 25 MHz oscillator is 40 ns
entity speaker is
port (
CLK: in std_logic;
HPERIOD: in std_logic_vector(24 downto 0);
PLAY: in std_logic;
PIN: out std_logic
);
end speaker;
architecture Behavioral of speaker is
begin
process (CLK)
variable sout: std_logic := '0';
variable prescaler: std_logic_vector(24 downto 0) := (others => '0');
begin
if CLK'event and CLK = '1' then
if PLAY = '1' then
if prescaler >= HPERIOD then
sout := not sout;
prescaler := (others => '0');
end if;
prescaler := prescaler + 1;
else
sout := '0';
prescaler := (others => '0');
end if;
end if;
PIN <= sout;
end process;
end Behavioral;

959
usage_statistics_webtalk.html
View file

File diff suppressed because it is too large Load diff

24
vga.vhd
View file

@ -7,11 +7,10 @@ entity vga is
port ( port (
CLK : in std_logic; CLK : in std_logic;
LED : out std_logic_vector(7 downto 0);
IRGB : in std_logic_vector(7 downto 0); IRGB : in std_logic_vector(7 downto 0);
RGB : out std_logic_vector(7 downto 0); RGB : out std_logic_vector(7 downto 0);
FRAME: out std_logic;
W : out std_logic; W : out std_logic;
X : out std_logic_vector(9 downto 0); X : out std_logic_vector(9 downto 0);
Y : out std_logic_vector(9 downto 0); Y : out std_logic_vector(9 downto 0);
@ -26,19 +25,19 @@ architecture Behavioral of vga is
signal vert : std_logic_vector(9 downto 0); signal vert : std_logic_vector(9 downto 0);
begin begin
process (CLK) begin process (CLK)
variable fout : std_logic := '0';
begin
if CLK'event and CLK = '1' then if CLK'event and CLK = '1' then
-- 144 and 784 if (horiz >= 145) and (horiz < 788)
if (horiz >= 146) and (horiz < 788) and (vert >= 35) and (vert < 514) then
-- 39 and 519
and (vert >= 32) and (vert < 519) then
W <= '1'; W <= '1';
RGB <= IRGB; RGB <= IRGB;
X <= horiz - 144 + 1; X <= horiz - 146 + 1;
Y <= vert - 39 + 1; Y <= vert - 34 + 1;
else else
W <= '0'; W <= '0';
RGB <= "11100011"; RGB <= "00000000";
end if; end if;
if (horiz > 0) and (horiz < 97) then if (horiz > 0) and (horiz < 97) then
@ -60,8 +59,13 @@ process (CLK) begin
end if; end if;
if (vert = 521) then if (vert = 521) then
fout := '1';
vert <= (others => '0'); vert <= (others => '0');
else
fout := '0';
end if; end if;
FRAME <= fout;
end if; end if;
end process; end process;

8
webtalk_pn.xml
View file

@ -3,10 +3,10 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools. <!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases. The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.--> This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Thu Feb 21 20:21:12 2013"> <application name="pn" timeStamp="Fri Feb 22 15:42:14 2013">
<section name="Project Information" visible="false"> <section name="Project Information" visible="false">
<property name="ProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="project"/> <property name="ProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="project"/>
<property name="ProjectIteration" value="58" type="project"/> <property name="ProjectIteration" value="133" type="project"/>
<property name="ProjectFile" value="C:/fpga/pong/pong.xise" type="project"/> <property name="ProjectFile" value="C:/fpga/pong/pong.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2013-02-15T19:54:09" type="project"/> <property name="ProjectCreationTimestamp" value="2013-02-15T19:54:09" type="project"/>
</section> </section>
@ -25,7 +25,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/> <property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2013-02-15T19:54:09" type="design"/> <property name="PROP_intProjectCreationTimestamp" value="2013-02-15T19:54:09" type="design"/>
<property name="PROP_intWbtProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="design"/> <property name="PROP_intWbtProjectID" value="7EC662CDC4744D03A066C93D40613B74" type="design"/>
<property name="PROP_intWbtProjectIteration" value="58" type="process"/> <property name="PROP_intWbtProjectIteration" value="133" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/> <property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/> <property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_lockPinsUcfFile" value="changed" type="process"/> <property name="PROP_lockPinsUcfFile" value="changed" type="process"/>
@ -39,7 +39,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_DevSpeed" value="-5" type="design"/> <property name="PROP_DevSpeed" value="-5" type="design"/>
<property name="PROP_PreferredLanguage" value="Verilog" type="design"/> <property name="PROP_PreferredLanguage" value="Verilog" type="design"/>
<property name="FILE_UCF" value="1" type="source"/> <property name="FILE_UCF" value="1" type="source"/>
<property name="FILE_VHDL" value="2" type="source"/> <property name="FILE_VHDL" value="4" type="source"/>
</section> </section>
</application> </application>
</document> </document>

BIN
xlnx_auto_0_xdb/cst.xbcd
View file

Binary file not shown.

10
xst/work/hdllib.ref
View file

@ -1,4 +1,6 @@
AR vga behavioral C:/fpga/pong/vga.vhd sub00/vhpl03 1361499657 AR speaker behavioral C:/fpga/pong/speaker.vhd sub00/vhpl05 1361569314
AR main behavioral C:/fpga/pong/main.vhd sub00/vhpl01 1361499659 AR vga behavioral C:/fpga/pong/vga.vhd sub00/vhpl03 1361569316
EN main NULL C:/fpga/pong/main.vhd sub00/vhpl00 1361499658 AR main behavioral C:/fpga/pong/main.vhd sub00/vhpl01 1361569318
EN vga NULL C:/fpga/pong/vga.vhd sub00/vhpl02 1361499656 EN main NULL C:/fpga/pong/main.vhd sub00/vhpl00 1361569317
EN vga NULL C:/fpga/pong/vga.vhd sub00/vhpl02 1361569315
EN speaker NULL C:/fpga/pong/speaker.vhd sub00/vhpl04 1361569313

23
xst/work/hdpdeps.ref
View file

@ -1,11 +1,16 @@
V3 7 V3 11
FL C:/fpga/pong/main.vhd 2013/02/21.18:24:26 P.15xf FL C:/fpga/pong/main.vhd 2013/02/22.15:41:49 P.15xf
EN work/main 1361499658 FL C:/fpga/pong/main.vhd PB ieee/std_logic_1164 1335251622 \ EN work/main 1361569317 FL C:/fpga/pong/main.vhd PB ieee/std_logic_1164 1335251622 \
PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625 PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625
AR work/main/Behavioral 1361499659 \ AR work/main/Behavioral 1361569318 \
FL C:/fpga/pong/main.vhd EN work/main 1361499658 CP vga FL C:/fpga/pong/main.vhd EN work/main 1361569317 CP speaker CP vga
FL C:/fpga/pong/vga.vhd 2013/02/21.20:20:49 P.15xf FL C:/fpga/pong/speaker.vhd 2013/02/22.15:16:32 P.15xf
EN work/vga 1361499656 FL C:/fpga/pong/vga.vhd PB ieee/std_logic_1164 1335251622 \ EN work/speaker 1361569313 FL C:/fpga/pong/speaker.vhd PB ieee/std_logic_1164 1335251622 \
PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625 PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625
AR work/vga/Behavioral 1361499657 \ AR work/speaker/Behavioral 1361569314 \
FL C:/fpga/pong/vga.vhd EN work/vga 1361499656 FL C:/fpga/pong/speaker.vhd EN work/speaker 1361569313
FL C:/fpga/pong/vga.vhd 2013/02/22.13:16:43 P.15xf
EN work/vga 1361569315 FL C:/fpga/pong/vga.vhd PB ieee/std_logic_1164 1335251622 \
PB ieee/std_logic_arith 1335251623 PB ieee/STD_LOGIC_UNSIGNED 1335251625
AR work/vga/Behavioral 1361569316 \
FL C:/fpga/pong/vga.vhd EN work/vga 1361569315

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